Simulation Results: lc_ctrl/volatile_unlock_disabled

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.23 %
  • code
  • 82.92 %
  • assert
  • 93.85 %
  • func
  • 90.93 %
  • line
  • 97.20 %
  • branch
  • 93.41 %
  • cond
  • 79.22 %
  • toggle
  • 84.00 %
  • FSM
  • 60.75 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.370s 73.156us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.100s 17.965us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.930s 19.181us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.920s 221.666us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 45.044us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.600s 31.980us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.930s 19.181us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 45.044us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.560s 118.256us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.620s 653.607us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.080s 13.911us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.520s 137.201us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.830s 692.528us 1 1 100.00
lc_errors 0 1 0.00
lc_ctrl_errors 2.130s 244.033us 0 1 0.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 8.830s 692.528us 1 1 100.00
lc_ctrl_prog_failure 2.520s 137.201us 1 1 100.00
lc_ctrl_errors 2.130s 244.033us 0 1 0.00
lc_ctrl_security_escalation 6.500s 1155.000us 1 1 100.00
lc_ctrl_jtag_state_failure 18.580s 1414.897us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.900s 185.806us 1 1 100.00
lc_ctrl_jtag_errors 39.210s 3255.171us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.720s 1028.486us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.490s 871.170us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.900s 185.806us 1 1 100.00
lc_ctrl_jtag_errors 39.210s 3255.171us 1 1 100.00
lc_ctrl_jtag_access 1.870s 119.504us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.110s 2656.017us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.330s 348.407us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.800s 244.851us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.800s 2930.300us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.780s 1928.338us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.080s 63.922us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.750s 1383.777us 1 1 100.00
lc_ctrl_jtag_alert_test 1.530s 704.178us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.500s 668.248us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.190s 76.733us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 151.720s 29624.156us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.210s 90.368us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.960s 23.846us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.960s 23.846us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.100s 17.965us 1 1 100.00
lc_ctrl_csr_rw 0.930s 19.181us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 45.044us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 27.928us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.100s 17.965us 1 1 100.00
lc_ctrl_csr_rw 0.930s 19.181us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 45.044us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 27.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.410s 124.342us 1 1 100.00
lc_ctrl_tl_intg_err 2.340s 830.267us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.340s 830.267us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.620s 653.607us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.830s 692.528us 1 1 100.00
lc_ctrl_sec_cm 6.410s 124.342us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.830s 692.528us 1 1 100.00
lc_ctrl_sec_cm 6.410s 124.342us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.830s 692.528us 1 1 100.00
lc_ctrl_sec_cm 6.410s 124.342us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.830s 692.528us 1 1 100.00
lc_ctrl_sec_cm 6.410s 124.342us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.830s 692.528us 1 1 100.00
lc_ctrl_sec_cm 6.410s 124.342us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.830s 692.528us 1 1 100.00
lc_ctrl_sec_cm 6.410s 124.342us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.830s 692.528us 1 1 100.00
lc_ctrl_sec_cm 6.410s 124.342us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.830s 692.528us 1 1 100.00
lc_ctrl_sec_cm 6.410s 124.342us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.500s 1155.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.560s 118.256us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.490s 871.170us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.530s 3856.244us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.530s 3856.244us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.030s 755.895us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.380s 7194.413us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.380s 7194.413us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 14.510s 4585.171us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_errors 74351764020066119082295015707209787285495403429848498881678349831032912808115 618
UVM_INFO @ 244032757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---