Simulation Results: lc_ctrl/volatile_unlock_enabled

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.71 %
  • code
  • 83.85 %
  • assert
  • 94.69 %
  • func
  • 93.59 %
  • line
  • 97.09 %
  • branch
  • 93.52 %
  • cond
  • 79.20 %
  • toggle
  • 85.90 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.310s 160.611us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.920s 26.083us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.770s 45.500us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.890s 219.107us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 84.106us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.040s 17.552us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.770s 45.500us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 84.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.570s 317.998us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.690s 581.532us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.900s 34.842us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.200s 182.181us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.810s 265.607us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.960s 371.783us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.810s 265.607us 1 1 100.00
lc_ctrl_prog_failure 2.200s 182.181us 1 1 100.00
lc_ctrl_errors 7.960s 371.783us 1 1 100.00
lc_ctrl_security_escalation 4.170s 228.933us 1 1 100.00
lc_ctrl_jtag_state_failure 21.030s 10444.369us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.770s 365.687us 1 1 100.00
lc_ctrl_jtag_errors 13.630s 4922.153us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.960s 730.806us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.890s 703.400us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.770s 365.687us 1 1 100.00
lc_ctrl_jtag_errors 13.630s 4922.153us 1 1 100.00
lc_ctrl_jtag_access 3.780s 754.426us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.300s 4260.704us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.530s 64.589us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.860s 55.849us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.260s 3451.815us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.320s 1846.552us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.560s 219.324us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.490s 567.958us 1 1 100.00
lc_ctrl_jtag_alert_test 1.650s 251.312us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.320s 295.791us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.010s 50.844us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 111.650s 10013.905us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.500s 407.142us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.470s 609.772us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.470s 609.772us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 26.083us 1 1 100.00
lc_ctrl_csr_rw 0.770s 45.500us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 84.106us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.080s 27.095us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 26.083us 1 1 100.00
lc_ctrl_csr_rw 0.770s 45.500us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 84.106us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.080s 27.095us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.660s 651.635us 1 1 100.00
lc_ctrl_tl_intg_err 2.350s 50.044us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.350s 50.044us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.690s 581.532us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.810s 265.607us 1 1 100.00
lc_ctrl_sec_cm 5.660s 651.635us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.810s 265.607us 1 1 100.00
lc_ctrl_sec_cm 5.660s 651.635us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.810s 265.607us 1 1 100.00
lc_ctrl_sec_cm 5.660s 651.635us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.810s 265.607us 1 1 100.00
lc_ctrl_sec_cm 5.660s 651.635us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.810s 265.607us 1 1 100.00
lc_ctrl_sec_cm 5.660s 651.635us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.810s 265.607us 1 1 100.00
lc_ctrl_sec_cm 5.660s 651.635us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.810s 265.607us 1 1 100.00
lc_ctrl_sec_cm 5.660s 651.635us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.810s 265.607us 1 1 100.00
lc_ctrl_sec_cm 5.660s 651.635us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.170s 228.933us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.570s 317.998us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.890s 703.400us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.140s 1568.567us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.140s 1568.567us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.250s 959.894us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.580s 894.775us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.580s 894.775us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 19.730s 3790.964us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 97956404025424889481548587834875905089066892638901951697999657678199196480570 5222
UVM_INFO @ 3790964091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---