Simulation Results: otp_ctrl

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.09 %
  • code
  • 77.47 %
  • assert
  • 94.64 %
  • func
  • 74.15 %
  • line
  • 88.42 %
  • branch
  • 83.26 %
  • cond
  • 90.07 %
  • toggle
  • 82.90 %
  • FSM
  • 42.71 %
Validation stages
V1
88.89%
V2
90.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.040s 111.539us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.420s 1998.544us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.820s 94.950us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.480s 50.486us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.810s 1648.696us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.640s 184.344us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.270s 26.285us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.480s 50.486us 1 1 100.00
otp_ctrl_csr_aliasing 4.640s 184.344us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.140s 144.199us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.200s 74.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.620s 5994.093us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.400s 698.238us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 3.520s 215.793us 1 1 100.00
otp_ctrl_check_fail 9.900s 470.583us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 9.710s 5358.418us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 30.450s 28015.624us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 17.120s 1224.141us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 14.000s 723.004us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.420s 1709.735us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 5.960s 390.676us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 8.070s 548.712us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 65.780s 11881.998us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.210s 77.222us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.160s 809.774us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.390s 118.886us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.390s 118.886us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.820s 94.950us 1 1 100.00
otp_ctrl_csr_rw 1.480s 50.486us 1 1 100.00
otp_ctrl_csr_aliasing 4.640s 184.344us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.830s 90.370us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.820s 94.950us 1 1 100.00
otp_ctrl_csr_rw 1.480s 50.486us 1 1 100.00
otp_ctrl_csr_aliasing 4.640s 184.344us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.830s 90.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
otp_ctrl_tl_intg_err 10.100s 10487.602us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 10.100s 10487.602us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.420s 1998.544us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.420s 1998.544us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
otp_ctrl_macro_errs 5.960s 390.676us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
otp_ctrl_macro_errs 5.960s 390.676us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.210s 180.632us 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.400s 698.238us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 9.900s 470.583us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 30.450s 28015.624us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 30.450s 28015.624us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 30.450s 28015.624us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 30.450s 28015.624us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 30.450s 28015.624us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.420s 1998.544us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 30.450s 28015.624us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.420s 1998.544us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 117.620s 25804.803us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 9.710s 5358.418us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.420s 1998.544us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.420s 1998.544us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 5.960s 390.676us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.300s 3566.318us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 32.290s 13190.164us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 28409334573444351471950932001734931405422038535861381810749019379620696819497 12687
UVM_INFO @ 470583208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 82430515837662389961831344692749275679558539048605534202904995186046073805077 5409
UVM_INFO @ 390676095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 95956723408720890129700617023064963693290466195026748742896229811482253407196 264
UVM_INFO @ 13190163774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 44825327193005054433022716431398289550432965114324078394274187553180414382072 92
UVM_INFO @ 26284564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---