Simulation Results: pwrmgr

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.15 %
  • code
  • 91.15 %
  • assert
  • 98.96 %
  • func
  • 98.35 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.33 %
  • toggle
  • 90.96 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.610s 36.829us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.830s 72.050us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.800s 20.321us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.440s 396.076us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.790s 20.403us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.940s 81.012us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.800s 20.321us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 20.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.760s 647.480us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.760s 647.480us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.890s 31.536us 1 1 100.00
pwrmgr_lowpower_invalid 0.670s 72.450us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.670s 57.917us 1 1 100.00
pwrmgr_reset_invalid 0.710s 254.080us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.670s 57.917us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.060s 357.732us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.740s 158.906us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 2.150s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.690s 123.774us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.620s 23.679us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.560s 151.768us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.560s 151.768us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.830s 72.050us 1 1 100.00
pwrmgr_csr_rw 0.800s 20.321us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 20.403us 1 1 100.00
pwrmgr_same_csr_outstanding 0.830s 29.352us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.830s 72.050us 1 1 100.00
pwrmgr_csr_rw 0.800s 20.321us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 20.403us 1 1 100.00
pwrmgr_same_csr_outstanding 0.830s 29.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.960s 248.914us 1 1 100.00
pwrmgr_sec_cm 1.590s 615.343us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.590s 615.343us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.590s 615.343us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.960s 248.914us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.130s 834.045us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.060s 357.732us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.470s 1265.374us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.900s 50.786us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.640s 29.933us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.590s 615.343us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.590s 615.343us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.590s 615.343us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.700s 124.248us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.790s 76.913us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.920s 250.413us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.800s 20.321us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.800s 20.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.790s 104.936us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 7.750s 2861.263us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_disable_rom_integrity_check 62454114807852968693925400802572036320290480454843523053474173223010016857683 106
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitAckPwrUp 1 test run
pwrmgr_reset_invalid 26218294659966816785799746422106425674946010085150428155634425119377448774559 103
UVM_INFO @ 254079876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---