Simulation Results: rom_ctrl/32kb

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.00 %
  • code
  • 91.91 %
  • assert
  • 96.66 %
  • func
  • 96.42 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 95.10 %
  • toggle
  • 92.37 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.110s 137.957us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.360s 168.249us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.650s 514.180us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.990s 367.976us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.740s 811.753us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.280s 135.413us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.650s 514.180us 1 1 100.00
rom_ctrl_csr_aliasing 3.740s 811.753us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.270s 384.601us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.170s 167.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.850s 130.158us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.310s 577.749us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.880s 2125.176us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.920s 545.044us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.290s 292.906us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.290s 292.906us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.360s 168.249us 1 1 100.00
rom_ctrl_csr_rw 3.650s 514.180us 1 1 100.00
rom_ctrl_csr_aliasing 3.740s 811.753us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.830s 126.038us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.360s 168.249us 1 1 100.00
rom_ctrl_csr_rw 3.650s 514.180us 1 1 100.00
rom_ctrl_csr_aliasing 3.740s 811.753us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.830s 126.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 9.220s 145.876us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.390s 3312.181us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 102.700s 1118.479us 1 1 100.00
rom_ctrl_tl_intg_err 24.610s 412.095us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 102.700s 1118.479us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 102.700s 1118.479us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 9.220s 145.876us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 9.220s 145.876us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 9.220s 145.876us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 9.220s 145.876us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 9.220s 145.876us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 102.700s 1118.479us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 102.700s 1118.479us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.110s 137.957us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.110s 137.957us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.110s 137.957us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.610s 412.095us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 9.220s 145.876us 0 1 0.00
rom_ctrl_kmac_err_chk 6.880s 2125.176us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 9.220s 145.876us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 9.220s 145.876us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 9.220s 145.876us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.390s 3312.181us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 102.700s 1118.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 57.380s 4638.427us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 77742706864357756866433044975655259463869925833181489133126592457037014107447 79
UVM_INFO @ 130158363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 40261761276576245976429585738695144621063504034004757729568374447498823230056 82
UVM_INFO @ 145875755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---