Simulation Results: rom_ctrl/64kb

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.94 %
  • code
  • 98.45 %
  • assert
  • 97.53 %
  • func
  • 97.85 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 97.92 %
  • toggle
  • 95.21 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.730s 730.810us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.770s 365.939us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.760s 835.886us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.530s 205.462us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.770s 726.244us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 9.650s 2214.725us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.760s 835.886us 1 1 100.00
rom_ctrl_csr_aliasing 5.770s 726.244us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.250s 209.022us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.220s 295.522us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.130s 172.075us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 17.420s 1167.849us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.780s 565.949us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.800s 629.075us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.190s 649.737us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.190s 649.737us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.770s 365.939us 1 1 100.00
rom_ctrl_csr_rw 6.760s 835.886us 1 1 100.00
rom_ctrl_csr_aliasing 5.770s 726.244us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.530s 544.913us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.770s 365.939us 1 1 100.00
rom_ctrl_csr_rw 6.760s 835.886us 1 1 100.00
rom_ctrl_csr_aliasing 5.770s 726.244us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.530s 544.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.440s 19980.792us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.630s 6940.298us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 462.330s 1431.695us 1 1 100.00
rom_ctrl_tl_intg_err 100.990s 4380.410us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 462.330s 1431.695us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 462.330s 1431.695us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.440s 19980.792us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.440s 19980.792us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.440s 19980.792us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.440s 19980.792us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.440s 19980.792us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 462.330s 1431.695us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 462.330s 1431.695us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.730s 730.810us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.730s 730.810us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.730s 730.810us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 100.990s 4380.410us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.440s 19980.792us 1 1 100.00
rom_ctrl_kmac_err_chk 14.780s 565.949us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.440s 19980.792us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.440s 19980.792us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 140.440s 19980.792us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.630s 6940.298us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 462.330s 1431.695us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 66.890s 9567.645us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 44224843186419900368278544393077571611681695530413181953977252750831114042012 79
UVM_INFO @ 172074518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---