Simulation Results: rstmgr

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.00 %
  • code
  • 99.32 %
  • assert
  • 98.66 %
  • func
  • 96.02 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.96 %
  • toggle
  • 98.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.160s 138.374us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.150s 96.416us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.860s 83.489us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.670s 382.955us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.480s 157.407us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.040s 149.163us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.860s 83.489us 1 1 100.00
rstmgr_csr_aliasing 1.480s 157.407us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.730s 126.648us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.510s 194.524us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.380s 304.327us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.620s 1612.039us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.620s 1612.039us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.620s 1612.039us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.620s 1612.039us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 11.760s 5261.113us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.060s 82.362us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.830s 499.740us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.830s 499.740us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.150s 96.416us 1 1 100.00
rstmgr_csr_rw 0.860s 83.489us 1 1 100.00
rstmgr_csr_aliasing 1.480s 157.407us 1 1 100.00
rstmgr_same_csr_outstanding 0.940s 137.822us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.150s 96.416us 1 1 100.00
rstmgr_csr_rw 0.860s 83.489us 1 1 100.00
rstmgr_csr_aliasing 1.480s 157.407us 1 1 100.00
rstmgr_same_csr_outstanding 0.940s 137.822us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.110s 16817.967us 1 1 100.00
rstmgr_tl_intg_err 3.100s 928.251us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.110s 16817.967us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.110s 16817.967us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.100s 928.251us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.900s 106.831us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.590s 1403.912us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.120s 304.453us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.110s 16817.967us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.860s 83.489us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.860s 83.489us 1 1 100.00