Simulation Results: rv_timer

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.33 %
  • code
  • 94.66 %
  • assert
  • 98.73 %
  • func
  • 95.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.940s 491.840us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.650s 68.802us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.830s 78.571us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.750s 124.016us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.770s 17.659us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.780s 24.954us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.830s 78.571us 1 1 100.00
rv_timer_csr_aliasing 0.770s 17.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.750s 210.692us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.320s 1885.999us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 1.750s 1196.366us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 1.750s 1196.366us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.600s 65.164us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.600s 65.054us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 13.063us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.340s 235.562us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.340s 235.562us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 68.802us 1 1 100.00
rv_timer_csr_rw 0.830s 78.571us 1 1 100.00
rv_timer_csr_aliasing 0.770s 17.659us 1 1 100.00
rv_timer_same_csr_outstanding 0.740s 27.904us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 68.802us 1 1 100.00
rv_timer_csr_rw 0.830s 78.571us 1 1 100.00
rv_timer_csr_aliasing 0.770s 17.659us 1 1 100.00
rv_timer_same_csr_outstanding 0.740s 27.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.830s 77.823us 1 1 100.00
rv_timer_tl_intg_err 0.990s 493.321us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.990s 493.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.660s 43.101us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.670s 56.789us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 13.910s 2055.382us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 108037465643063632004359313294174608214990330085809664473022863307892596244326 75
UVM_INFO @ 56788731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 110487737105227033667851210721499768814647062968850437675143126423910679611362 75
UVM_INFO @ 210692175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---