Simulation Results: spi_device/1r1w

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.59 %
  • code
  • 91.27 %
  • assert
  • 95.40 %
  • func
  • 70.09 %
  • line
  • 98.84 %
  • branch
  • 98.11 %
  • cond
  • 95.74 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 3.970s 524.902us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.930s 43.507us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.970s 133.331us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.610s 3892.974us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.630s 303.692us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.660s 399.887us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.970s 133.331us 1 1 100.00
spi_device_csr_aliasing 11.630s 303.692us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.880s 28.763us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.210s 70.129us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.910s 78.665us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.770s 6.009us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.770s 4.758us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.320s 161.769us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.320s 161.769us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 7.440s 9663.639us 1 1 100.00
spi_device_tpm_sts_read 0.790s 220.140us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 15.050s 2463.591us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.070s 4110.081us 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.850s 309.800us 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 1.850s 309.800us 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.700s 2611.375us 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.700s 2611.375us 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.700s 2611.375us 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.700s 2611.375us 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.700s 2611.375us 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 1.840s 52.140us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 4.090s 538.220us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 4.090s 538.220us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 4.090s 538.220us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.820s 301.191us 1 1 100.00
spi_device_read_buffer_direct 6.990s 857.683us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 4.090s 538.220us 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 213.710s 53424.643us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.120s 2609.612us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.120s 2609.612us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 4.920s 321.662us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 3.970s 524.902us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 89.870s 72388.927us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 291.290s 56549.337us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.820s 24.820us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.990s 17.167us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.910s 269.022us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.910s 269.022us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.930s 43.507us 1 1 100.00
spi_device_csr_rw 1.970s 133.331us 1 1 100.00
spi_device_csr_aliasing 11.630s 303.692us 1 1 100.00
spi_device_same_csr_outstanding 1.460s 325.104us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.930s 43.507us 1 1 100.00
spi_device_csr_rw 1.970s 133.331us 1 1 100.00
spi_device_csr_aliasing 11.630s 303.692us 1 1 100.00
spi_device_same_csr_outstanding 1.460s 325.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.930s 160.230us 1 1 100.00
spi_device_tl_intg_err 16.910s 1004.395us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 16.910s 1004.395us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 89478585040700332673277445693226022635165264321084388715792881984284565076417 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 4248502 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 4248502 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[956])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 72296377949682171572747744460479972575845644758638249773010358160941578381145 76
UVM_ERROR @ 2309933 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2ef [1011101111] vs 0x0 [0])
UVM_ERROR @ 2374933 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2a6 [1010100110] vs 0x0 [0])
UVM_ERROR @ 2413933 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x319 [1100011001] vs 0x0 [0])
UVM_ERROR @ 2463933 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x144 [101000100] vs 0x0 [0])