Simulation Results: spi_host

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.93 %
  • code
  • 95.03 %
  • assert
  • 95.09 %
  • func
  • 88.66 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 23.000s 6235.193us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 21.033us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 17.763us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 1464.187us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 31.746us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 35.729us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 17.763us 1 1 100.00
spi_host_csr_aliasing 1.000s 31.746us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 30.360us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 51.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 23.268us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 75.906us 1 1 100.00
spi_host_error_cmd 2.000s 47.731us 1 1 100.00
spi_host_event 14.000s 676.903us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 85.313us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 85.313us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 85.313us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 337.000s 36658.229us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 97.915us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 30.351us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 85.313us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 85.313us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 23.000s 6235.193us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 23.000s 6235.193us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 24.000s 6505.802us 1 1 100.00
spien 1 1 100.00
spi_host_spien 6.000s 907.565us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 128.000s 5990.768us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 10.000s 3309.833us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 75.906us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 41.794us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 78.763us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 202.175us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 202.175us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 21.033us 1 1 100.00
spi_host_csr_rw 1.000s 17.763us 1 1 100.00
spi_host_csr_aliasing 1.000s 31.746us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 53.966us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 21.033us 1 1 100.00
spi_host_csr_rw 1.000s 17.763us 1 1 100.00
spi_host_csr_aliasing 1.000s 31.746us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 53.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 350.481us 1 1 100.00
spi_host_sec_cm 1.000s 39.101us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 350.481us 1 1 100.00