Simulation Results: sram_ctrl/main

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 95.53 %
  • assert
  • 97.82 %
  • func
  • 94.60 %
  • block
  • 95.70 %
  • line
  • 96.38 %
  • branch
  • 93.53 %
  • toggle
  • 92.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 2301.155us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 14.039us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.243us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 101.745us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 65.430us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 379.187us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 12.243us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 65.430us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 230.000s 23385.347us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 76.000s 6714.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 28.000s 28163.201us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 180.000s 75759.052us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 159.000s 18247.539us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 44.000s 11023.502us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 11.000s 3603.108us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 13.000s 2721.703us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 6.000s 4713.290us 1 1 100.00
sram_ctrl_partial_access_b2b 164.000s 55791.887us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 3.000s 691.686us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 692.468us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 2553.250us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1822.541us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 365.668us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 139.000s 8939.343us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.175us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 375.999us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 375.999us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.039us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.243us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 65.430us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.948us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 14.039us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.243us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 65.430us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 19.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 14692.009us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 793.534us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 393.823us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 793.534us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 393.823us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1822.541us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 1822.541us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.243us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 13.000s 2721.703us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 2721.703us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 2721.703us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 11.000s 3603.108us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 3925.693us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 14692.009us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 8280.975us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 2301.155us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 2301.155us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 13.000s 2721.703us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 793.534us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 11.000s 3603.108us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 793.534us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 793.534us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 2301.155us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 793.534us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 58.000s 2758.530us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 96394675516757547021808191194761743885160189708695535320079812551955691537660 86
UVM_INFO @ 691685817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 28045483251035390798540430330429701849978148919537301478810551324923646358585 86
UVM_INFO @ 692467764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 110258148387004883865088627514005601218032358349302740445618516512507196818760 86
UVM_INFO @ 2553249659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---