Simulation Results: sysrst_ctrl

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.58 %
  • code
  • 91.25 %
  • assert
  • 90.52 %
  • func
  • 62.96 %
  • line
  • 96.09 %
  • branch
  • 96.66 %
  • cond
  • 92.80 %
  • toggle
  • 99.54 %
  • FSM
  • 71.15 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.610s 2136.326us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.070s 2468.565us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.500s 2220.608us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.810s 2295.951us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 9.510s 4031.006us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.220s 2074.500us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 37.610s 76466.160us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.200s 2580.462us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.770s 2103.011us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.220s 2074.500us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.200s 2580.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 12.290s 135622.368us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 23.490s 26840.574us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.450s 3097.802us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.990s 3368.225us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.470s 2513.037us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.850s 2155.089us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 10.110s 5354.755us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.180s 2611.232us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 3.630s 6435.797us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 14.350s 31924.195us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 201.890s 119571.171us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.840s 2034.804us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 0.990s 2240.972us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.610s 2281.905us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.610s 2281.905us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 9.510s 4031.006us 1 1 100.00
sysrst_ctrl_csr_rw 2.220s 2074.500us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.200s 2580.462us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.870s 8100.426us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 9.510s 4031.006us 1 1 100.00
sysrst_ctrl_csr_rw 2.220s 2074.500us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.200s 2580.462us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.870s 8100.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 19.990s 22033.248us 1 1 100.00
sysrst_ctrl_tl_intg_err 23.060s 22313.139us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 23.060s 22313.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.020s 20470.087us 1 1 100.00