Simulation Results: uart

 
21/07/2026 15:30:33 DVSim: v1.49.12 sha: 93c75a6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.88 %
  • code
  • 91.05 %
  • assert
  • 98.56 %
  • func
  • 62.03 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 94.17 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 6.260s 5889.862us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.620s 20.237us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 12.559us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.400s 453.144us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.990s 121.971us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.870s 79.617us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 12.559us 1 1 100.00
uart_csr_aliasing 0.990s 121.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 5.410s 5787.804us 1 1 100.00
parity 2 2 100.00
uart_smoke 6.260s 5889.862us 1 1 100.00
uart_tx_rx 5.410s 5787.804us 1 1 100.00
parity_error 2 2 100.00
uart_intr 92.010s 372732.641us 1 1 100.00
uart_rx_parity_err 14.300s 43499.245us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 5.410s 5787.804us 1 1 100.00
uart_intr 92.010s 372732.641us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 17.500s 28618.021us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 8.820s 99608.002us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 22.840s 46872.337us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 92.010s 372732.641us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 92.010s 372732.641us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 92.010s 372732.641us 1 1 100.00
perf 1 1 100.00
uart_perf 116.220s 21179.273us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 4.320s 9165.414us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 4.320s 9165.414us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.210s 461.545us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.760s 3570.554us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.000s 1124.570us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 16.020s 7461.094us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 68.580s 67844.485us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 310.740s 320104.814us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.870s 37.821us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.650s 70.081us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 0.870s 86.316us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 0.870s 86.316us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.620s 20.237us 1 1 100.00
uart_csr_rw 0.590s 12.559us 1 1 100.00
uart_csr_aliasing 0.990s 121.971us 1 1 100.00
uart_same_csr_outstanding 0.710s 150.586us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.620s 20.237us 1 1 100.00
uart_csr_rw 0.590s 12.559us 1 1 100.00
uart_csr_aliasing 0.990s 121.971us 1 1 100.00
uart_same_csr_outstanding 0.710s 150.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.980s 86.395us 1 1 100.00
uart_tl_intg_err 1.120s 354.748us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.120s 354.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 38.850s 7514.111us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 84731866455776826991547652340208304959594404899440018188633178863687333659691 74
UVM_ERROR @ 85365925 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 87063896 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 87063896 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 93470351 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0