Simulation Results: adc_ctrl

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.73 %
  • code
  • 92.13 %
  • assert
  • 92.06 %
  • func
  • 12.99 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 85.98 %
  • toggle
  • 99.29 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.880s 5955.206us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.660s 825.693us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.970s 360.892us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 54.490s 25091.132us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.430s 1120.559us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.020s 601.666us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.970s 360.892us 1 1 100.00
adc_ctrl_csr_aliasing 2.430s 1120.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.970s 282.137us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.770s 298.057us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.110s 396.703us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.080s 370.798us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.880s 487.672us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 1.070s 497.404us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.050s 365.337us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.810s 476.916us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.080s 4620.443us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 61.820s 43211.960us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 152.800s 107702.597us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 0.940s 694.825us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.960s 332.510us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.720s 394.626us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.260s 673.128us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.260s 673.128us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.660s 825.693us 1 1 100.00
adc_ctrl_csr_rw 0.970s 360.892us 1 1 100.00
adc_ctrl_csr_aliasing 2.430s 1120.559us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.840s 2816.213us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.660s 825.693us 1 1 100.00
adc_ctrl_csr_rw 0.970s 360.892us 1 1 100.00
adc_ctrl_csr_aliasing 2.430s 1120.559us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.840s 2816.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 1.840s 3540.738us 1 1 100.00
adc_ctrl_tl_intg_err 2.830s 5027.269us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.830s 5027.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.780s 878.266us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 114247092537005232930269699627674882236133583329917109897764378053635769065288 386
UVM_INFO @ 282137194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 90477028481917797499620035541588532450579135544543467032067269669003177866254 386
UVM_INFO @ 298057146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 21028219054445155702924487257127594068727242155333403622809552350289354037569 386
UVM_INFO @ 396703024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 80534498905946296359397189164302155452773090392825539698208515190543063562194 386
UVM_INFO @ 370798374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 99886331945837458142652202097312549112859417703758695666574470559161539861033 386
UVM_INFO @ 487672074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 20837876481639761128409892893697077118732672042270786707360595108792364285990 386
UVM_INFO @ 497403763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 30455800697607361112413007431680460710906694108492219741716882840251469947060 386
UVM_INFO @ 476915519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 13904683771826383776974709648298468588246148601877069553741499865936287369638 386
UVM_INFO @ 365336615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 79235264897094659598188380007482155308163956489553398817742008029407901883042 392
UVM_INFO @ 878265641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 8919332440055991954247493333574364153551394159306229686165333334859491523392 387
UVM_INFO @ 694824722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---