Simulation Results: aes/masked

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.27 %
  • code
  • 94.09 %
  • assert
  • 98.23 %
  • func
  • 72.47 %
  • block
  • 95.02 %
  • line
  • 96.02 %
  • branch
  • 89.04 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 146.213us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 223.017us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 94.730us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 57.016us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 4723.423us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 514.032us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 63.074us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 57.016us 1 1 100.00
aes_csr_aliasing 2.000s 514.032us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 223.017us 1 1 100.00
aes_config_error 3.000s 108.028us 1 1 100.00
aes_stress 2.000s 99.396us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 223.017us 1 1 100.00
aes_config_error 3.000s 108.028us 1 1 100.00
aes_stress 2.000s 99.396us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 99.396us 1 1 100.00
aes_b2b 8.000s 185.857us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 99.396us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 223.017us 1 1 100.00
aes_config_error 3.000s 108.028us 1 1 100.00
aes_stress 2.000s 99.396us 1 1 100.00
aes_alert_reset 2.000s 127.348us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 229.937us 1 1 100.00
aes_config_error 3.000s 108.028us 1 1 100.00
aes_alert_reset 2.000s 127.348us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 151.221us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 1150.695us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 127.348us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 99.396us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 99.396us 1 1 100.00
aes_sideload 2.000s 95.026us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 76.326us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 11.000s 1490.544us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 79.630us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 236.283us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 236.283us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 94.730us 1 1 100.00
aes_csr_rw 2.000s 57.016us 1 1 100.00
aes_csr_aliasing 2.000s 514.032us 1 1 100.00
aes_same_csr_outstanding 2.000s 108.613us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 94.730us 1 1 100.00
aes_csr_rw 2.000s 57.016us 1 1 100.00
aes_csr_aliasing 2.000s 514.032us 1 1 100.00
aes_same_csr_outstanding 2.000s 108.613us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 116.541us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 4.000s 119.813us 0 1 0.00
aes_control_fi 1.000s 71.140us 1 1 100.00
aes_cipher_fi 2.000s 61.561us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 85.556us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 85.556us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 85.556us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 85.556us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 84.371us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 1003.444us 1 1 100.00
aes_tl_intg_err 2.000s 131.523us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 131.523us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 127.348us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 85.556us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 85.556us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 223.017us 1 1 100.00
aes_stress 2.000s 99.396us 1 1 100.00
aes_alert_reset 2.000s 127.348us 1 1 100.00
aes_core_fi 3.000s 217.595us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 108.028us 1 1 100.00
aes_stress 2.000s 99.396us 1 1 100.00
aes_core_fi 3.000s 217.595us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 85.556us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 63.992us 1 1 100.00
aes_stress 2.000s 99.396us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 99.396us 1 1 100.00
aes_sideload 2.000s 95.026us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 63.992us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 63.992us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 63.992us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 63.992us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 63.992us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 99.396us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 99.396us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 119.813us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 119.813us 0 1 0.00
aes_control_fi 1.000s 71.140us 1 1 100.00
aes_cipher_fi 2.000s 61.561us 1 1 100.00
aes_ctr_fi 2.000s 65.610us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 119.813us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 119.813us 0 1 0.00
aes_control_fi 1.000s 71.140us 1 1 100.00
aes_cipher_fi 2.000s 61.561us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 61.561us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 119.813us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 119.813us 0 1 0.00
aes_control_fi 1.000s 71.140us 1 1 100.00
aes_ctr_fi 2.000s 65.610us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 119.813us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 119.813us 0 1 0.00
aes_control_fi 1.000s 71.140us 1 1 100.00
aes_cipher_fi 2.000s 61.561us 1 1 100.00
aes_ctr_fi 2.000s 65.610us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 127.348us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 119.813us 0 1 0.00
aes_control_fi 1.000s 71.140us 1 1 100.00
aes_cipher_fi 2.000s 61.561us 1 1 100.00
aes_ctr_fi 2.000s 65.610us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 119.813us 0 1 0.00
aes_control_fi 1.000s 71.140us 1 1 100.00
aes_cipher_fi 2.000s 61.561us 1 1 100.00
aes_ctr_fi 2.000s 65.610us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 119.813us 0 1 0.00
aes_control_fi 1.000s 71.140us 1 1 100.00
aes_ctr_fi 2.000s 65.610us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 119.813us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 119.813us 0 1 0.00
aes_control_fi 1.000s 71.140us 1 1 100.00
aes_cipher_fi 2.000s 61.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 8.389us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 88984549372007677725592658830304912224951147201929225878002966776200592773693 7789
UVM_INFO @ 116540845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 86472556759657122194468979957201204319934350008576688729219270979138024416167 19486
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 25493292626268591980876002909165968586118694747042710486553011915017077953132 138
UVM_INFO @ 8388941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---