Simulation Results: aes/unmasked

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.08 %
  • code
  • 90.08 %
  • assert
  • 97.73 %
  • func
  • 73.42 %
  • block
  • 90.37 %
  • line
  • 91.93 %
  • branch
  • 81.52 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 113.338us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 71.515us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 77.941us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 86.245us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 185.372us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 859.560us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 64.476us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 86.245us 1 1 100.00
aes_csr_aliasing 4.000s 859.560us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 71.515us 1 1 100.00
aes_config_error 3.000s 249.224us 1 1 100.00
aes_stress 2.000s 120.194us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 71.515us 1 1 100.00
aes_config_error 3.000s 249.224us 1 1 100.00
aes_stress 2.000s 120.194us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 120.194us 1 1 100.00
aes_b2b 2.000s 126.897us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 120.194us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 71.515us 1 1 100.00
aes_config_error 3.000s 249.224us 1 1 100.00
aes_stress 2.000s 120.194us 1 1 100.00
aes_alert_reset 2.000s 139.952us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 70.404us 1 1 100.00
aes_config_error 3.000s 249.224us 1 1 100.00
aes_alert_reset 2.000s 139.952us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 78.257us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 461.760us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 139.952us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 120.194us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 120.194us 1 1 100.00
aes_sideload 2.000s 89.120us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 131.949us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 12.000s 401.114us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 55.140us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 128.990us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 128.990us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 77.941us 1 1 100.00
aes_csr_rw 2.000s 86.245us 1 1 100.00
aes_csr_aliasing 4.000s 859.560us 1 1 100.00
aes_same_csr_outstanding 2.000s 87.788us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 77.941us 1 1 100.00
aes_csr_rw 2.000s 86.245us 1 1 100.00
aes_csr_aliasing 4.000s 859.560us 1 1 100.00
aes_same_csr_outstanding 2.000s 87.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 11.090us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 155.186us 0 1 0.00
aes_control_fi 2.000s 118.362us 1 1 100.00
aes_cipher_fi 2.000s 88.138us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 71.949us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 71.949us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 71.949us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 71.949us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 472.318us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1395.095us 1 1 100.00
aes_tl_intg_err 1.000s 124.674us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 124.674us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 139.952us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 71.949us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 71.949us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 71.515us 1 1 100.00
aes_stress 2.000s 120.194us 1 1 100.00
aes_alert_reset 2.000s 139.952us 1 1 100.00
aes_core_fi 1.000s 75.109us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 249.224us 1 1 100.00
aes_stress 2.000s 120.194us 1 1 100.00
aes_core_fi 1.000s 75.109us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 71.949us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 57.388us 1 1 100.00
aes_stress 2.000s 120.194us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 120.194us 1 1 100.00
aes_sideload 2.000s 89.120us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 57.388us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 57.388us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 57.388us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 57.388us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 57.388us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 120.194us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 120.194us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 155.186us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 155.186us 0 1 0.00
aes_control_fi 2.000s 118.362us 1 1 100.00
aes_cipher_fi 2.000s 88.138us 1 1 100.00
aes_ctr_fi 2.000s 70.189us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 155.186us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 155.186us 0 1 0.00
aes_control_fi 2.000s 118.362us 1 1 100.00
aes_cipher_fi 2.000s 88.138us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 88.138us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 155.186us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 155.186us 0 1 0.00
aes_control_fi 2.000s 118.362us 1 1 100.00
aes_ctr_fi 2.000s 70.189us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 155.186us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 155.186us 0 1 0.00
aes_control_fi 2.000s 118.362us 1 1 100.00
aes_cipher_fi 2.000s 88.138us 1 1 100.00
aes_ctr_fi 2.000s 70.189us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 139.952us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 155.186us 0 1 0.00
aes_control_fi 2.000s 118.362us 1 1 100.00
aes_cipher_fi 2.000s 88.138us 1 1 100.00
aes_ctr_fi 2.000s 70.189us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 155.186us 0 1 0.00
aes_control_fi 2.000s 118.362us 1 1 100.00
aes_cipher_fi 2.000s 88.138us 1 1 100.00
aes_ctr_fi 2.000s 70.189us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 155.186us 0 1 0.00
aes_control_fi 2.000s 118.362us 1 1 100.00
aes_ctr_fi 2.000s 70.189us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 155.186us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 155.186us 0 1 0.00
aes_control_fi 2.000s 118.362us 1 1 100.00
aes_cipher_fi 2.000s 88.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 52.192us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 74677302182142795655667641368126293137662388441635196252919481229934752473449 707
UVM_INFO @ 11089639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 79647474356977493640822603718362340745728376845140245666106724062030733105706 228
UVM_INFO @ 52191688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 60796377537555458482711761316997190176792952101273112029723167719808926043019 3270
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0