Simulation Results: alert_handler

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.48 %
  • code
  • 90.71 %
  • assert
  • 98.21 %
  • func
  • 79.51 %
  • line
  • 99.66 %
  • branch
  • 97.92 %
  • cond
  • 90.77 %
  • toggle
  • 91.00 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 21.250s 1290.168us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.670s 260.742us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.630s 125.493us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 151.240s 2520.515us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 36.150s 640.011us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.420s 131.693us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.630s 125.493us 1 1 100.00
alert_handler_csr_aliasing 36.150s 640.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 85.080s 5491.827us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 23.450s 1916.846us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1854.910s 55528.662us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 9.490s 341.835us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 21.250s 1290.168us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 12.590s 756.931us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 28.130s 1970.014us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 36.100s 1419.821us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1725.730s 46738.666us 1 1 100.00
alert_handler_lpg_stub_clk 424.680s 8064.213us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1452.820s 40631.211us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.220s 197.629us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.550s 44.064us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.230s 42.940us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 14.370s 1359.232us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 14.370s 1359.232us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.670s 260.742us 1 1 100.00
alert_handler_csr_rw 3.630s 125.493us 1 1 100.00
alert_handler_csr_aliasing 36.150s 640.011us 1 1 100.00
alert_handler_same_csr_outstanding 26.410s 1273.307us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.670s 260.742us 1 1 100.00
alert_handler_csr_rw 3.630s 125.493us 1 1 100.00
alert_handler_csr_aliasing 36.150s 640.011us 1 1 100.00
alert_handler_same_csr_outstanding 26.410s 1273.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 57.290s 1146.278us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 57.290s 1146.278us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 57.290s 1146.278us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 57.290s 1146.278us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 182.270s 2700.958us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 7.390s 697.038us 1 1 100.00
alert_handler_tl_intg_err 23.370s 2388.869us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 23.370s 2388.869us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 57.290s 1146.278us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 21.250s 1290.168us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 21.250s 1290.168us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 21.250s 1290.168us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 21.250s 1290.168us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 9.490s 341.835us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1725.730s 46738.666us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 9.490s 341.835us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1854.910s 55528.662us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1854.910s 55528.662us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 7.390s 697.038us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 7.390s 697.038us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 7.390s 697.038us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 7.390s 697.038us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 7.390s 697.038us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.390s 697.038us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.390s 697.038us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.390s 697.038us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 7.390s 697.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 5.470s 450.958us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 29474425103566829933115560108635229103572596395454858193512393019929537363930 93
UVM_INFO @ 1419820506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 73028588993694943737735000415043055929485283615878115409941850953683293944008 198
UVM_INFO @ 197628691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 32475777930442694017707295125848631658427351654711637956008003175514234910286 83
UVM_INFO @ 450957896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---