Simulation Results

Simulation Results: chip

22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
72.91 %

code
84.04 %

assert
97.37 %

func
37.32 %

line
94.19 %

branch
93.50 %

cond
88.81 %

toggle
86.57 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		75.09%
V2S		100.00%
V3		57.69%
unmapped		63.64%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	172.370s	2781.148us	1	1	100.00
	chip_sw_example_rom	93.280s	2545.459us	1	1	100.00
	chip_sw_example_manufacturer	173.350s	3755.581us	1	1	100.00
	chip_sw_example_concurrency	147.440s	3820.794us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	220.970s	4467.079us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	232.560s	4810.361us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	263.380s	4680.548us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	3050.310s	27366.238us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	384.790s	7063.272us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	3050.310s	27366.238us	1	1	100.00
	chip_csr_rw	232.560s	4810.361us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	6.490s	50.419us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	330.880s	4663.522us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	330.880s	4663.522us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	330.880s	4663.522us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	346.080s	4366.220us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	346.080s	4366.220us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	405.110s	5408.164us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	383.710s	5621.274us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	378.970s	5224.214us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1868.490s	13643.884us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	473.590s	5300.192us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	356.020s	5071.571us	1	1	100.00

208/277 passed

75.09 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	191.470s	6528.580us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	191.470s	6528.580us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	225.520s	4262.634us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	210.290s	4032.736us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	175.120s	4228.684us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	122.090s	3487.150us	1	1	100.00
	chip_tap_straps_testunlock0	276.090s	5538.084us	1	1	100.00
	chip_tap_straps_rma	281.980s	4871.816us	1	1	100.00
	chip_tap_straps_prod	693.680s	10925.325us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	449.840s	7619.985us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	449.840s	7619.985us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	616.920s	8148.099us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	663.840s	8695.084us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	351.120s	4437.437us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	538.290s	6340.162us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4189.080s	19628.909us	1	1	100.00
	chip_sw_aes_enc_jitter_en	178.060s	3264.677us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	774.270s	8142.215us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	180.920s	3411.928us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	708.660s	7468.697us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	181.900s	3646.183us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	402.690s	5381.104us	1	1	100.00
	chip_sw_clkmgr_jitter	189.850s	3369.461us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	224.870s	4428.934us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	724.800s	11345.506us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	254.750s	5952.388us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	224.430s	3747.841us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	254.750s	5952.388us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	177.070s	3336.240us	1	1	100.00
	chip_sw_aes_smoketest	149.680s	3389.486us	1	1	100.00
	chip_sw_aon_timer_smoketest	194.550s	3113.442us	1	1	100.00
	chip_sw_clkmgr_smoketest	194.180s	3115.198us	1	1	100.00
	chip_sw_csrng_smoketest	167.600s	2946.956us	1	1	100.00
	chip_sw_entropy_src_smoketest	1206.790s	8357.664us	1	1	100.00
	chip_sw_gpio_smoketest	186.340s	3179.124us	1	1	100.00
	chip_sw_hmac_smoketest	256.210s	4082.877us	1	1	100.00
	chip_sw_kmac_smoketest	170.920s	3120.941us	1	1	100.00
	chip_sw_otbn_smoketest	607.400s	6034.448us	1	1	100.00
	chip_sw_pwrmgr_smoketest	369.690s	6551.338us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	277.390s	7618.137us	1	1	100.00
	chip_sw_rv_plic_smoketest	181.940s	3804.369us	1	1	100.00
	chip_sw_rv_timer_smoketest	205.870s	3760.871us	1	1	100.00
	chip_sw_rstmgr_smoketest	146.500s	3341.515us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	157.740s	2887.739us	1	1	100.00
	chip_sw_uart_smoketest	207.400s	4431.918us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	231.870s	3629.579us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	356.170s	4827.207us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7987.280s	60628.962us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3319.390s	15873.420us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	34.333s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	1166.300s	16239.028us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	667.950s	15382.889us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7260.430s	54907.763us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7197.330s	55386.583us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	66.290s	2669.824us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	66.290s	2669.824us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	3050.310s	27366.238us	1	1	100.00
	chip_same_csr_outstanding	2491.130s	27773.586us	1	1	100.00
	chip_csr_hw_reset	220.970s	4467.079us	1	1	100.00
	chip_csr_rw	232.560s	4810.361us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	3050.310s	27366.238us	1	1	100.00
	chip_same_csr_outstanding	2491.130s	27773.586us	1	1	100.00
	chip_csr_hw_reset	220.970s	4467.079us	1	1	100.00
	chip_csr_rw	232.560s	4810.361us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	53.050s	1988.491us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	6.390s	42.696us	1	1	100.00
	xbar_smoke_large_delays	44.680s	8118.294us	1	1	100.00
	xbar_smoke_slow_rsp	49.880s	5786.680us	1	1	100.00
	xbar_random_zero_delays	21.770s	362.801us	1	1	100.00
	xbar_random_large_delays	280.620s	47568.548us	1	1	100.00
	xbar_random_slow_rsp	101.330s	11418.566us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	24.880s	309.727us	1	1	100.00
	xbar_error_and_unmapped_addr	31.970s	1259.410us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	11.360s	358.398us	1	1	100.00
	xbar_error_and_unmapped_addr	31.970s	1259.410us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	49.430s	1013.609us	1	1	100.00
	xbar_access_same_device_slow_rsp	87.130s	11271.686us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	23.590s	401.384us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	164.690s	6675.011us	1	1	100.00
	xbar_stress_all_with_error	107.420s	4662.984us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	47.940s	345.324us	1	1	100.00
	xbar_stress_all_with_reset_error	169.230s	897.405us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3319.390s	15873.420us	1	1	100.00
rom_e2e_shutdown_output				0	1	0.00
	rom_e2e_shutdown_output	580.700s	14570.749us	0	1	0.00
rom_e2e_shutdown_exception_c				0	1	0.00
	rom_e2e_shutdown_exception_c	434.570s	5668.811us	0	1	0.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	52.359s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	10.505s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	10.520s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.403s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	7.557s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	171.230s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	74.602s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	24.678s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.154s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	8.040s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	126.483s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	69.671s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	148.192s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	62.068s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	42.718s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	21.170s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	23.360s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	29.620s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	24.410s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	21.070s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	22.190s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	20.710s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	20.430s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	21.820s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	20.300s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	20.030s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	20.590s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.250s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.880s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.120s	10.220us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	62.946s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	74.530s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	81.185s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	78.817s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	66.445s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	5951.290s	30370.730us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	6184.360s	31649.090us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	3304.650s	19664.073us	0	1	0.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3412.090s	17004.720us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3113.750s	35804.217us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3113.750s	35804.217us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	152.610s	3394.945us	1	1	100.00
	chip_sw_aes_enc_jitter_en	178.060s	3264.677us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	163.670s	2853.367us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	164.340s	3251.417us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1330.210s	10056.497us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	168.140s	3226.807us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	369.780s	5221.223us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	455.560s	7398.668us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	567.480s	5438.580us	1	1	100.00
	chip_plic_all_irqs_10	343.470s	4221.460us	1	1	100.00
	chip_plic_all_irqs_20	371.810s	5225.786us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	202.520s	3721.390us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1311.210s	13528.281us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	341.030s	5125.022us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	152.820s	2914.056us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.140s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1336.820s	11144.310us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	879.170s	7375.541us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	748.730s	8394.412us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8465.990s	255955.367us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	302.660s	4899.294us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	369.690s	6551.338us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	302.660s	4899.294us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	423.170s	7732.605us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	423.170s	7732.605us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	317.220s	8363.334us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	390.380s	5652.681us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	567.810s	6587.283us	1	1	100.00
	chip_sw_aes_idle	164.340s	3251.417us	1	1	100.00
	chip_sw_hmac_enc_idle	248.670s	3882.229us	1	1	100.00
	chip_sw_kmac_idle	157.130s	3999.445us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	311.520s	5209.027us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	371.290s	4826.835us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	362.850s	5541.281us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	232.270s	5108.614us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	861.880s	13884.447us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	411.340s	4219.344us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	383.550s	5447.600us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	447.390s	4613.166us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	395.090s	5471.282us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	366.990s	3900.211us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	370.010s	5233.816us	1	1	100.00
	chip_sw_ast_clk_outputs	616.920s	8148.099us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	738.810s	12790.551us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	447.390s	4613.166us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	395.090s	5471.282us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	351.120s	4437.437us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	538.290s	6340.162us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4189.080s	19628.909us	1	1	100.00
	chip_sw_aes_enc_jitter_en	178.060s	3264.677us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	774.270s	8142.215us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	180.920s	3411.928us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	708.660s	7468.697us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	181.900s	3646.183us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	402.690s	5381.104us	1	1	100.00
	chip_sw_clkmgr_jitter	189.850s	3369.461us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	154.000s	3024.431us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	387.710s	5643.274us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	560.740s	7864.875us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4241.080s	25663.615us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	161.800s	4486.813us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	219.850s	4142.228us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	658.520s	9076.207us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	176.350s	3434.542us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	386.910s	6372.660us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1217.890s	27376.302us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	2295.520s	19421.907us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	616.920s	8148.099us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	449.670s	5775.419us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	312.530s	4331.050us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	455.560s	7398.668us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1336.820s	11144.310us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2162.620s	24942.820us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	295.940s	5509.586us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	509.250s	8374.576us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	190.330s	4021.623us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2249.610s	13848.939us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	140.510s	2881.167us	1	1	100.00
	chip_sw_edn_entropy_reqs	760.300s	7592.755us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	140.510s	2881.167us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2162.620s	24942.820us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	177.180s	4010.365us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1415.830s	24097.154us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	503.090s	6652.335us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	538.290s	6340.162us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	429.620s	4836.829us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	351.120s	4437.437us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3635.670s	45146.514us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1415.830s	24097.154us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	294.330s	4175.812us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1675.740s	13759.190us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	215.000s	3091.923us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3635.670s	45146.514us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	215.000s	3091.923us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	215.000s	3091.923us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	215.000s	3091.923us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	215.000s	3091.923us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	455.560s	7398.668us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	140.380s	4725.730us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	614.060s	6097.905us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	433.220s	7773.668us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	433.220s	7773.668us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	170.090s	3525.084us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	180.920s	3411.928us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	248.670s	3882.229us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1384.640s	10772.255us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1616.440s	12026.629us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	382.100s	5189.044us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	544.830s	6197.865us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	367.320s	4682.647us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	275.520s	5124.749us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1675.740s	13759.190us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	708.660s	7468.697us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1228.510s	9302.716us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1330.210s	10056.497us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	3932.090s	20018.450us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	139.710s	2642.653us	1	1	100.00
	chip_sw_kmac_mode_kmac	224.750s	3519.725us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	181.900s	3646.183us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1675.740s	13759.190us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	388.130s	8342.551us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	202.520s	3883.130us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1030.740s	7792.156us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	157.130s	3999.445us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	369.780s	5221.223us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	122.090s	3487.150us	1	1	100.00
	chip_tap_straps_rma	281.980s	4871.816us	1	1	100.00
	chip_tap_straps_prod	693.680s	10925.325us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	215.740s	4075.477us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	388.130s	8342.551us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	388.130s	8342.551us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	388.130s	8342.551us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1083.690s	10991.168us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	215.000s	3091.923us	0	1	0.00
	chip_sw_flash_rma_unlocked	3635.670s	45146.514us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	227.680s	3632.368us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	583.830s	9228.856us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	543.350s	9845.536us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	428.050s	6821.260us	0	1	0.00
	chip_sw_lc_ctrl_transition	388.130s	8342.551us	1	1	100.00
	chip_sw_keymgr_key_derivation	1675.740s	13759.190us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	412.370s	10669.427us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	602.040s	10260.169us	1	1	100.00
	chip_prim_tl_access	140.380s	4725.730us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	738.810s	12790.551us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	411.340s	4219.344us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	383.550s	5447.600us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	447.390s	4613.166us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	395.090s	5471.282us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	366.990s	3900.211us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	370.010s	5233.816us	1	1	100.00
	chip_tap_straps_dev	122.090s	3487.150us	1	1	100.00
	chip_tap_straps_rma	281.980s	4871.816us	1	1	100.00
	chip_tap_straps_prod	693.680s	10925.325us	1	1	100.00
	chip_rv_dm_lc_disabled	83.420s	3102.086us	0	1	0.00
chip_lc_scrap				3	4	75.00
	chip_sw_lc_ctrl_rma_to_scrap	226.470s	4993.617us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	111.740s	4029.929us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	755.490s	27669.895us	0	1	0.00
	chip_sw_lc_ctrl_rand_to_scrap	206.520s	3530.945us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1943.670s	42946.170us	1	1	100.00
	chip_rv_dm_lc_disabled	83.420s	3102.086us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	744.270s	13977.665us	0	1	0.00
	chip_sw_lc_walkthrough_prod	842.470s	12936.844us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	795.690s	14236.400us	1	1	100.00
	chip_sw_lc_walkthrough_rma	465.680s	9162.549us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1943.670s	42946.170us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	85.520s	2520.584us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	76.730s	2989.450us	1	1	100.00
	rom_volatile_raw_unlock	42.485s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	4086.840s	17471.516us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	4189.080s	19628.909us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	567.810s	6587.283us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	567.810s	6587.283us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	567.810s	6587.283us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	358.380s	4911.264us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	388.130s	8342.551us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1415.830s	24097.154us	1	1	100.00
	chip_sw_otbn_mem_scramble	358.380s	4911.264us	1	1	100.00
	chip_sw_keymgr_key_derivation	1675.740s	13759.190us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	410.340s	5521.513us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	190.490s	3045.662us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1415.830s	24097.154us	1	1	100.00
	chip_sw_otbn_mem_scramble	358.380s	4911.264us	1	1	100.00
	chip_sw_keymgr_key_derivation	1675.740s	13759.190us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	410.340s	5521.513us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	190.490s	3045.662us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	388.130s	8342.551us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	367.630s	6050.363us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	215.740s	4075.477us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	227.680s	3632.368us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	583.830s	9228.856us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	543.350s	9845.536us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	428.050s	6821.260us	0	1	0.00
	chip_sw_lc_ctrl_transition	388.130s	8342.551us	1	1	100.00
	chip_prim_tl_access	140.380s	4725.730us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	140.380s	4725.730us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	860.410s	8353.962us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	296.180s	8706.195us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	1206.150s	28608.895us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	228.240s	7491.302us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	380.950s	7503.846us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	375.090s	7378.311us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1226.140s	25058.216us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	314.190s	7378.314us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	423.170s	7732.605us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	832.160s	12398.919us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	389.960s	6505.388us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	296.180s	8706.195us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	334.710s	6656.225us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	237.310s	5562.604us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	339.360s	8246.970us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	194.310s	4374.775us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	648.610s	12124.640us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	815.330s	9958.633us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1094.890s	16255.982us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1739.810s	31956.810us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	200.940s	3353.944us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	455.560s	7398.668us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	412.370s	10669.427us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	412.370s	10669.427us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1094.890s	16255.982us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	648.610s	12124.640us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	389.960s	6505.388us	1	1	100.00
	chip_sw_pwrmgr_smoketest	369.690s	6551.338us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	337.880s	6959.121us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	453.630s	7342.127us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	294.520s	6150.232us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1311.210s	13528.281us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	179.620s	3773.309us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	455.560s	7398.668us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	879.170s	7375.541us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	488.660s	5297.061us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	523.010s	6384.810us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	235.850s	4143.884us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	190.490s	3045.662us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	453.630s	7342.127us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	453.630s	7342.127us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	157.040s	3175.638us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	611.440s	10697.219us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	842.110s	13408.861us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	337.880s	6959.121us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	213.820s	4443.308us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	1343.360s	13613.671us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	281.980s	4871.816us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	83.420s	3102.086us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	567.480s	5438.580us	1	1	100.00
	chip_plic_all_irqs_10	343.470s	4221.460us	1	1	100.00
	chip_plic_all_irqs_20	371.810s	5225.786us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	170.060s	3089.031us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	187.010s	3506.072us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3319.390s	15873.420us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	220.630s	4039.781us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	263.530s	4231.690us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	259.090s	3860.099us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	248.340s	3801.749us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	410.340s	5521.513us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	402.690s	5381.104us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	448.560s	8624.905us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	436.300s	9637.344us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	602.040s	10260.169us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	455.560s	7398.668us	1	1	100.00
	chip_sw_data_integrity_escalation	449.840s	7619.985us	1	1	100.00
chip_sw_sysrst_ctrl_reset				1	2	50.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	815.330s	9958.633us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	868.670s	22659.540us	0	1	0.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	211.450s	3836.433us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	281.840s	4620.070us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	357.350s	5211.150us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				0	1	0.00
	chip_sw_sysrst_ctrl_reset	868.670s	22659.540us	0	1	0.00
chip_sw_sysrst_ctrl_sleep_reset				0	1	0.00
	chip_sw_sysrst_ctrl_reset	868.670s	22659.540us	0	1	0.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2077.120s	20374.998us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2077.120s	20374.998us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	383.170s	6932.888us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3113.750s	35804.217us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	171.310s	3704.458us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	177.580s	3586.990us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	309.610s	4603.056us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	386.690s	5079.904us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	981.740s	8632.536us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5405.280s	32211.753us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1991.490s	12475.435us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	174.490s	3183.358us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	245.240s	4511.975us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	98.260s	2725.604us	1	1	100.00

15/26 passed

57.69 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9695.120s	68966.539us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1128.800s	6791.909us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	506.090s	7438.845us	0	1	0.00
	rom_e2e_jtag_debug_dev	220.060s	5474.674us	0	1	0.00
	rom_e2e_jtag_debug_rma	206.480s	4665.150us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	84.910s	2324.248us	0	1	0.00
	rom_e2e_jtag_inject_dev	81.470s	2311.672us	0	1	0.00
	rom_e2e_jtag_inject_rma	70.260s	2682.025us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	52.396s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	314.200s	4720.833us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	344.850s	3981.961us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	1122.140s	7263.396us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	917.780s	7825.655us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	266.300s	3272.862us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	654.880s	5992.586us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	82.380s	3114.079us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	239.070s	4497.987us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				0	1	0.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	283.980s	6711.238us	0	1	0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	342.440s	5281.458us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1094.890s	16255.982us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	506.090s	7438.845us	0	1	0.00
	rom_e2e_jtag_debug_dev	220.060s	5474.674us	0	1	0.00
	rom_e2e_jtag_debug_rma	206.480s	4665.150us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				0	1	0.00
	chip_sw_rv_dm_access_after_escalation_reset	196.550s	4573.235us	0	1	0.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	455.560s	7398.668us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5337.350s	39381.929us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5337.350s	39381.929us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	203.140s	4569.493us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	346.080s	4366.220us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3125.830s	20049.919us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	239.620s	4155.641us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	22.400s	10.100us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	6.330s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	179.420s	4139.437us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	216.580s	4354.541us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	253.080s	4029.206us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	8.501s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	257.900s	4658.577us	1	1	100.00
	ate_bootstrap_flash_erase	633.070s	10010.380us	0	1	0.00
	ate_bootstrap_one_frame	6527.390s	44395.789us	1	1	100.00
	ate_bootstrap_disjoint	9002.780s	80015.129us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	13206170601976152823845530095389678126443431574964256190168978065744733042136	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	62119925519097053667555653184853650682447326483968492164538333102757869967477	None	Another command (pid=381177) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=418062) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=393605) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	84677887233112332397661102452200782526524682554678526225812872860854300589594	None	Another command (pid=393215) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=582188) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=592063) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	64848934016394587960473492771652571565039142196542549630612820294019464346238	None	Another command (pid=582188) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=592063) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=590807) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	16139544087241357039157854770133924018612125462214349773567005574031373513986	None	Another command (pid=581014) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=490569) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=602218) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	22583923141636291296182391399752872875908493342175628154762745623790963107118	None	---- STDERR ---- Another command (pid=589180) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	95843563262294122136279952158068933478297019894104086594717632421393332312368	None	Another command (pid=664907) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=677806) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=653034) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	68564094439975273329487840673695972266781434301248301623054343104608371609339	None	Another command (pid=477995) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=616547) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=642989) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	110672667327765880191621344659145135873971237167439048854844972173019220818522	None	Another command (pid=581014) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=490569) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=602218) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	107923670130932369645521979313427852954175007308737429257953211098274497546590	None	Another command (pid=478395) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=470395) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=472515) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	109363164113728150914562600595642764353653801685708872990784922033195405153762	None	---- STDERR ---- Another command (pid=575617) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=470395) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	57992443100588645735561179867010586935052235831275575867000617410743568408802	None	---- STDERR ---- Another command (pid=568987) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	66190116004752331806801704806549537689794755646908994934151302688594213836998	None	Another command (pid=502991) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=474293) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=456993) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	18211653650185322735272573451539179308424094490867825302827293882643065153503	None	Another command (pid=750916) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=757827) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=761113) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	15942134778981970839873629186171539812950881326975836555865397181817158755421	None	Another command (pid=474293) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=456993) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=478395) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	113393432928779822198562496242121936967090755473758817792677518142354105478141	None	Another command (pid=468135) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=567516) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=423592) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	58864987685283744879249106178005730016340822838988625082737549270393696287707	None	Another command (pid=393605) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=447635) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=472388) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	60349336779106633499992491836246310623633998763362445897596129727280602415157	None	Another command (pid=476432) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=473834) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=522177) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	21696837764481791053603571317145183102393349533371872966950557490883464402000	None	Another command (pid=456993) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=478395) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=575617) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	108405137514666516617840311350369525405180447719531243902421903170059152872015	None	Another command (pid=590807) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=589761) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=573237) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	104138841038340968953112373156557501108861610506593759164033694564157846871331	None	Another command (pid=423592) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=401674) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=491397) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	115512207133337899118609809201005898913857827364645865864449092066652302584754	None	Another command (pid=418062) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=393605) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=447635) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	42779750864533034732056959289804678060432990826442681029487268874749471050687	None	---- STDERR ---- Another command (pid=381177) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	67524138852138918507527246096454670023261843823882009517269387581534863182338	None	Another command (pid=418062) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=393605) is running. Waiting for it to complete on the server (server_pid=266098)... Another command (pid=410245) is running. Waiting for it to complete on the server (server_pid=266098)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				7 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	56802166880813734094277536277566903689126751568256772931763957140920497336355	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	90169843018274080462689311863622130323435275863815574214038512682854600807467	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	20142804419939497170284291580394913639492748870238472051319926118026700737325	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	9181872348094673116413502340347436435958827407592813670090715132904591356068	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	108456046366440364336180414217110992013825819391752914687496081026881678031701	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	20490474856674292897089548699313086536081103688342137272790782057860878562381	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	98717976638034104019392566690614241961286189226493037583256418082350886357241	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
Offending '(rstreqs[*] && (reset_cause == HwReq))'				6 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	30327905778225375144665591877409584892419581392303040730517569411896570817031	344	UVM_ERROR @ 12124.640000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 12124.640000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	29500709133289545041433925475364026868954873928166794929306729745357983003366	314	UVM_ERROR @ 7378.314000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7378.314000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	101687919927694235176047345911742702234038702470453181298911072926477563607994	325	UVM_ERROR @ 7503.846000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7503.846000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	78299261769585783995419522740140292722720183015910178308098318932340320563757	316	UVM_ERROR @ 5562.603500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 5562.603500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sysrst_ctrl_reset	17063604807189435923765229256692737470367614517317708774751456150822049451333	334	UVM_ERROR @ 22659.540000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 22659.540000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	77758699176347202234665493224836074649734131739959208545866431816093779512649	319	UVM_ERROR @ 7732.605000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7732.605000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	62843146353874714070734943307114354747247552894291326928923290381967803784438	368	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	39568368517529243684172246039210846225963258335682441071014732739836514335172	364	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	33821094030780629888959891943678074653848887065170056152359441626100459421371	364	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	47174959875915417169426087730307511554675102928244737512823082325741637796421	327	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	22217526104855033341297154856291198559418891759529951287346083031653213029709	325	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	21022300241772535911202404486830460952811849740411730885638738116499006742478	328	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	12736158666767681707002106507528655272223772250746532236672002754197970123899	369	UVM_INFO @ 13977.665461 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	99694002884242780800218524889868965456798747463791684661771589513213150278405	369	UVM_INFO @ 12936.843729 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	33988783045532315637233988931611376592929437517483887558086378791801389952041	341	UVM_INFO @ 9162.549330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	34876374805808985302516401519077484794179463159648016788989758849697377180699	326	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13572040370632551748108957982251820266620081422675724287934727133533077345719	325	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	66485893534430792011829680587121172629065033305850289310378521708287292709833	325	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_multistream	26591196317854850842348161112740901540090119650810835496016054998345684046424	367	UVM_INFO @ 12026.629318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	25503155993987147807964152956752517811527874702135976218371432170110024079697	334	UVM_INFO @ 20018.449679 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	73741283152277679914434092143360714270330144607729704038255112408777115912708	363	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	104667379277322868647728561004190098078127062059211673003821439390356177605660	325	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	28921708989909979352656306543835675621070316749045518993444581287721702549837	368	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	90781303871121743145483114166009538950283117174332078076858159980352811601734	327	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	5074675074718199459702755681058603468781338108357612858195175495259889263807	301	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	98613152684473804084124704001990601582173773372012197111465968255997619093101	327	UVM_INFO @ 4231.690050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	1929202659899474554208858819781875419515039092497157244392059176925623684379	309	UVM_INFO @ 3091.923240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	43879572940144462042476328897045121501738798199223510245284370358165566253326	342	UVM_INFO @ 6821.260254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	23598177888745509118280622184284207189599337559977412313144925734510003517699	316	UVM_ERROR @ 4497.986976 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 4497.986976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	72918804741290704699468608371542209923404923249115698236161548165516265376392	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_ctrl_test_locked0_to_scrap	13032253826885162448002157710883266679999108428963239294830702105790202410917	302	UVM_INFO @ 27669.895166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	15516116616535651904771946131413158692773055095734009753497956666301260479449	314	UVM_ERROR @ 8706.195122 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 8706.195122 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	2066872977507011703098075633150688148883255157483442633814799524434658561302	313	UVM_ERROR @ 4374.775004 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 4374.775004 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	50402298927788642904430929615571744633582122991613870516384552875943421914904	332	UVM_INFO @ 35804.216871 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:387)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	67315126143217985906276986539562310773779730649734889968943874111663593670989	307	UVM_INFO @ 3226.807496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	107517698356870025403233888306550094675964913444515877038187296508005549120434	308	UVM_INFO @ 2914.055857 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	40998347880850954606411610843437269142855059280618822191663868335080053302897	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_tl_errors	97715091219733130427867902463153754263564929911489804458327419636512139784507	217	TL item was: req: (cip_tl_seq_item@31466) { a_addr: 'h106cc a_data: 'h6616e8aa a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h4 a_user: 'h19ea7 d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2669.824109 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	102282562967596002719741992338904371780388892445612743466451286701824244594225	343	UVM_INFO @ 4720.832856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: *				1 test run
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	109633286472835988141548090856632266175588056268563048316120202661944164958008	316	UVM_INFO @ 6711.238474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.				1 test run
	chip_sw_rv_dm_access_after_wakeup	14461571290053227424601652469722605861552018916309399079886948236258170191174	329	UVM_INFO @ 13613.671128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)'				1 test run
	chip_sw_rv_dm_access_after_escalation_reset	16635031861611106477971050474408859389868675292877210879499143169167173483856	311	UVM_ERROR @ 4573.235364 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A UVM_INFO @ 4573.235364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	56314665146157328543874674255221331726687241731275434274354213375017973279106	215	UVM_INFO @ 3102.085605 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_idle_load	73574764368903380748324738211206349353214047655307655182757566280417601366011	318	UVM_INFO @ 16239.028464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_sleep_load	29095458358005450691624104734778472072143815603002996407553492983020499776610	337	UVM_INFO @ 15382.888564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	66932112382674143428150457758717458040558388241433402148070715426816180298395	327	UVM_INFO @ 8695.084085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	91544111678421998439714427974157253961876919928414682640942611813657532742003	272	UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_exception_c	99553288021247188939857486583663882804739691338020498676105080876515754251297	319	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 5668.811377 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred!				1 test run
	rom_e2e_shutdown_output	67030763450298953916895934397386516485151850848610620796732472695161080223106	309	UVM_INFO @ 14570.749316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	24174595543306436696185495626301080604845618119044871150737035849496539801479	325	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	29863812734598284430334302171894615263769650243558306531088231474469611600615	326	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5312476431203645367406501000860559118165319921852528164257340198175151403743	319	UVM_INFO @ 19664.073388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	107677849977825104062178629866980979413532323311216872969384838001772720257726	327	UVM_ERROR @ 4827.206832 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4827.206832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---