Simulation Results: clkmgr

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.84 %
  • code
  • 98.02 %
  • assert
  • 94.92 %
  • func
  • 85.59 %
  • line
  • 98.95 %
  • branch
  • 98.64 %
  • cond
  • 93.32 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.130s 185.149us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.750s 20.326us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.860s 61.484us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.550s 292.143us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.410s 63.339us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.920s 314.907us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.860s 61.484us 1 1 100.00
clkmgr_csr_aliasing 1.410s 63.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.760s 56.583us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.920s 59.570us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.910s 29.178us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.880s 127.298us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.130s 185.149us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 10.480s 2477.081us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.440s 1947.352us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 10.480s 2477.081us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 24.960s 6603.312us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.900s 20.185us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.810s 56.394us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.810s 56.394us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 20.326us 1 1 100.00
clkmgr_csr_rw 0.860s 61.484us 1 1 100.00
clkmgr_csr_aliasing 1.410s 63.339us 1 1 100.00
clkmgr_same_csr_outstanding 1.450s 206.543us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.750s 20.326us 1 1 100.00
clkmgr_csr_rw 0.860s 61.484us 1 1 100.00
clkmgr_csr_aliasing 1.410s 63.339us 1 1 100.00
clkmgr_same_csr_outstanding 1.450s 206.543us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 26.120s 10170.536us 0 1 0.00
clkmgr_tl_intg_err 1.300s 61.659us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 611.660s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 611.660s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 611.660s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 611.660s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.010s 124.051us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.300s 61.659us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 10.480s 2477.081us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.440s 1947.352us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 611.660s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.890s 45.720us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.760s 31.606us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.840s 65.296us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.790s 216.403us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.770s 54.447us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.860s 61.484us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 26.120s 10170.536us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.860s 61.484us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.860s 61.484us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 26.120s 10170.536us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.570s 876.636us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 50.540s 7685.211us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 22703602868960921282528962812175338192585334272542526270148288733620697894784 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 64711368652192717709533117531668373964811915369911142378758619784737931173718 145
UVM_INFO @ 10170535942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---