Simulation Results: edn/edn0

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.62 %
  • code
  • 80.19 %
  • assert
  • 96.10 %
  • func
  • 80.56 %
  • line
  • 97.23 %
  • branch
  • 90.79 %
  • cond
  • 86.42 %
  • toggle
  • 78.12 %
  • FSM
  • 48.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 25.360us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 14.360us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.820s 129.933us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.720s 328.226us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.520s 195.006us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.080s 116.284us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.820s 129.933us 1 1 100.00
edn_csr_aliasing 1.520s 195.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.840s 64.189us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.840s 64.189us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.840s 64.189us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.940s 22.841us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.220s 56.846us 1 1 100.00
errs 1 1 100.00
edn_err 0.800s 36.255us 1 1 100.00
disable 2 2 100.00
edn_disable 0.890s 14.128us 1 1 100.00
edn_disable_auto_req_mode 1.110s 286.472us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.940s 367.169us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.860s 147.543us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.860s 42.121us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.500s 25.425us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.500s 25.425us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 14.360us 1 1 100.00
edn_csr_rw 0.820s 129.933us 1 1 100.00
edn_csr_aliasing 1.520s 195.006us 1 1 100.00
edn_same_csr_outstanding 0.960s 56.870us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 14.360us 1 1 100.00
edn_csr_rw 0.820s 129.933us 1 1 100.00
edn_csr_aliasing 1.520s 195.006us 1 1 100.00
edn_same_csr_outstanding 0.960s 56.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.410s 770.576us 1 1 100.00
edn_tl_intg_err 1.370s 183.524us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 53.416us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.220s 56.846us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.410s 770.576us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.410s 770.576us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.410s 770.576us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.410s 770.576us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.220s 56.846us 1 1 100.00
edn_sec_cm 3.410s 770.576us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.220s 56.846us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.370s 183.524us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 31.400s 6509.131us 1 1 100.00