Simulation Results: edn/edn1

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.45 %
  • code
  • 82.41 %
  • assert
  • 98.44 %
  • func
  • 81.51 %
  • line
  • 98.25 %
  • branch
  • 93.94 %
  • cond
  • 90.23 %
  • toggle
  • 86.46 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.970s 42.307us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.920s 60.875us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.800s 54.342us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.810s 337.176us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 19.389us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.880s 38.196us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.800s 54.342us 1 1 100.00
edn_csr_aliasing 1.030s 19.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.040s 82.571us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.040s 82.571us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.040s 82.571us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.930s 21.671us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.020s 31.913us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 55.739us 1 1 100.00
disable 2 2 100.00
edn_disable 0.860s 21.499us 1 1 100.00
edn_disable_auto_req_mode 1.140s 29.265us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.900s 749.168us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 21.443us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.790s 32.074us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.660s 130.270us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.660s 130.270us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.920s 60.875us 1 1 100.00
edn_csr_rw 0.800s 54.342us 1 1 100.00
edn_csr_aliasing 1.030s 19.389us 1 1 100.00
edn_same_csr_outstanding 1.130s 34.431us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.920s 60.875us 1 1 100.00
edn_csr_rw 0.800s 54.342us 1 1 100.00
edn_csr_aliasing 1.030s 19.389us 1 1 100.00
edn_same_csr_outstanding 1.130s 34.431us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.900s 366.570us 1 1 100.00
edn_tl_intg_err 1.190s 55.975us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.830s 18.025us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.020s 31.913us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.900s 366.570us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.900s 366.570us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.900s 366.570us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.900s 366.570us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.020s 31.913us 1 1 100.00
edn_sec_cm 3.900s 366.570us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.020s 31.913us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.190s 55.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 58.560s 16329.341us 1 1 100.00