Simulation Results: flash_ctrl

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.47 %
  • code
  • 93.95 %
  • assert
  • 97.02 %
  • func
  • 95.45 %
  • line
  • 95.99 %
  • branch
  • 97.19 %
  • cond
  • 93.78 %
  • toggle
  • 95.71 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 46.990s 121.494us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 13.560s 33.199us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 23.030s 203.617us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 6.900s 324.491us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 28.830s 2090.249us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 20.840s 753.654us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.250s 111.008us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 6.900s 324.491us 1 1 100.00
flash_ctrl_csr_aliasing 20.840s 753.654us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.350s 31.663us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.750s 171.787us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 12.180s 43.412us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 47.840s 286.230us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1175.400s 342594.194us 1 1 100.00
flash_ctrl_hw_rma_reset 729.090s 760628.341us 1 1 100.00
flash_ctrl_lcmgr_intg 9.550s 126.189us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1581.370s 273974.150us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 169.000s 5846.109us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 11.270s 26.312us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1708.300s 137604.604us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 54.870s 1433.095us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.080s 38.245us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.680s 74.709us 1 1 100.00
flash_ctrl_re_evict 16.970s 111.171us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 163.730s 1401.220us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 163.730s 1401.220us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 169.710s 10440.754us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.110s 579.498us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 367.870s 385.246us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 294.130s 11530.623us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 396.260s 495.614us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 883.200s 1921.118us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.830s 78.240us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 128.040s 2684.085us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.910s 37.756us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.580s 28.129us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 265.570s 209.214us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 79.000s 10002.798us 1 1 100.00
flash_ctrl_otp_reset 59.120s 41.052us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1175.400s 342594.194us 1 1 100.00
interrupts 3 4 75.00
flash_ctrl_intr_rd 94.680s 8384.226us 0 1 0.00
flash_ctrl_intr_wr 46.320s 2927.090us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 88.270s 5911.516us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 103.650s 20951.324us 1 1 100.00
invalid_op 0 1 0.00
flash_ctrl_invalid_op 23.680s 452.368us 0 1 0.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 37.680s 2078.251us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.740s 37.825us 1 1 100.00
flash_ctrl_ro_derr 87.090s 1156.547us 1 1 100.00
flash_ctrl_rw_derr 132.050s 1463.446us 1 1 100.00
flash_ctrl_derr_detect 92.640s 634.014us 1 1 100.00
flash_ctrl_integrity 393.190s 21131.788us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.440s 37.751us 1 1 100.00
flash_ctrl_ro_serr 100.830s 1025.264us 1 1 100.00
flash_ctrl_rw_serr 141.320s 6357.296us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 39.360s 759.794us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 50.100s 918.035us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 111.940s 9806.806us 1 1 100.00
flash_ctrl_write_word_sweep 7.000s 83.496us 1 1 100.00
flash_ctrl_read_word_sweep 12.190s 105.802us 1 1 100.00
flash_ctrl_ro 81.000s 1587.801us 1 1 100.00
flash_ctrl_rw 367.600s 17931.168us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.520s 742.297us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 617.320s 253413.425us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 70.730s 10054.887us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.060s 75.212us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 7.920s 30.516us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.570s 67.890us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.570s 67.890us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 23.030s 203.617us 1 1 100.00
flash_ctrl_csr_rw 6.900s 324.491us 1 1 100.00
flash_ctrl_csr_aliasing 20.840s 753.654us 1 1 100.00
flash_ctrl_same_csr_outstanding 13.380s 198.625us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 23.030s 203.617us 1 1 100.00
flash_ctrl_csr_rw 6.900s 324.491us 1 1 100.00
flash_ctrl_csr_aliasing 20.840s 753.654us 1 1 100.00
flash_ctrl_same_csr_outstanding 13.380s 198.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 10.550s 85.039us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 10.550s 85.039us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 10.550s 85.039us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 10.550s 85.039us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 54.270s 455.176us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1763.460s 1810.601us 1 1 100.00
flash_ctrl_tl_intg_err 213.220s 374.626us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 213.220s 374.626us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 213.220s 374.626us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.570s 241.122us 1 1 100.00
flash_ctrl_wr_intg 11.940s 48.607us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 46.990s 121.494us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 59.120s 41.052us 1 1 100.00
flash_ctrl_disable 10.910s 37.756us 1 1 100.00
flash_ctrl_sec_info_access 46.080s 2527.080us 1 1 100.00
flash_ctrl_connect 7.580s 28.129us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.490s 22.616us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.900s 324.491us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 10.550s 85.039us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.900s 324.491us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 10.550s 85.039us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.900s 324.491us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 10.550s 85.039us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.910s 37.756us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.570s 241.122us 1 1 100.00
flash_ctrl_access_after_disable 6.220s 78.687us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 18.270s 28.217us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.910s 37.756us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.110s 579.498us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 367.600s 17931.168us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 141.320s 6357.296us 1 1 100.00
flash_ctrl_rw_derr 132.050s 1463.446us 1 1 100.00
flash_ctrl_integrity 393.190s 21131.788us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1175.400s 342594.194us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1763.460s 1810.601us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1763.460s 1810.601us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1763.460s 1810.601us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1763.460s 1810.601us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.800s 811.674us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.400s 22.979us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 11.090s 143.857us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1763.460s 1810.601us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1763.460s 1810.601us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1763.460s 1810.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 19.660s 41.534us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 227.720s 2180.003us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly 1 test run
flash_ctrl_invalid_op 72611095828889530274304063108798696624402253111255472668944445886978720471185 2825
UVM_INFO @ 452368.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *b3_59447b97:ffffffff_59447b* mismatch!! 1 test run
flash_ctrl_intr_rd 112417043136398798165246071192295004312853513590358287580641660019850582678905 108
UVM_INFO @ 8384225.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---