Simulation Results: hmac

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.36 %
  • code
  • 97.60 %
  • assert
  • 97.60 %
  • func
  • 42.89 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.39 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.190s 2890.577us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.710s 20.201us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.870s 29.976us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.550s 1216.340us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.310s 60.182us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 624.920s 276902.913us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.870s 29.976us 1 1 100.00
hmac_csr_aliasing 2.310s 60.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 67.260s 34380.563us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 44.020s 1508.908us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.200s 293.579us 1 1 100.00
hmac_test_sha384_vectors 437.630s 69068.306us 1 1 100.00
hmac_test_sha512_vectors 400.570s 72568.563us 1 1 100.00
hmac_test_hmac256_vectors 9.770s 1453.498us 1 1 100.00
hmac_test_hmac384_vectors 8.810s 1401.462us 1 1 100.00
hmac_test_hmac512_vectors 13.100s 2668.488us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.930s 5174.611us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 119.070s 9653.158us 1 1 100.00
error 1 1 100.00
hmac_error 69.940s 16805.300us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 55.750s 7818.310us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.190s 2890.577us 1 1 100.00
hmac_long_msg 67.260s 34380.563us 1 1 100.00
hmac_back_pressure 44.020s 1508.908us 1 1 100.00
hmac_datapath_stress 119.070s 9653.158us 1 1 100.00
hmac_burst_wr 12.930s 5174.611us 1 1 100.00
hmac_stress_all 1346.630s 154380.189us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.190s 2890.577us 1 1 100.00
hmac_long_msg 67.260s 34380.563us 1 1 100.00
hmac_back_pressure 44.020s 1508.908us 1 1 100.00
hmac_datapath_stress 119.070s 9653.158us 1 1 100.00
hmac_wipe_secret 55.750s 7818.310us 1 1 100.00
hmac_test_sha256_vectors 9.200s 293.579us 1 1 100.00
hmac_test_sha384_vectors 437.630s 69068.306us 1 1 100.00
hmac_test_sha512_vectors 400.570s 72568.563us 1 1 100.00
hmac_test_hmac256_vectors 9.770s 1453.498us 1 1 100.00
hmac_test_hmac384_vectors 8.810s 1401.462us 1 1 100.00
hmac_test_hmac512_vectors 13.100s 2668.488us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.190s 2890.577us 1 1 100.00
hmac_long_msg 67.260s 34380.563us 1 1 100.00
hmac_back_pressure 44.020s 1508.908us 1 1 100.00
hmac_datapath_stress 119.070s 9653.158us 1 1 100.00
hmac_burst_wr 12.930s 5174.611us 1 1 100.00
hmac_error 69.940s 16805.300us 1 1 100.00
hmac_wipe_secret 55.750s 7818.310us 1 1 100.00
hmac_test_sha256_vectors 9.200s 293.579us 1 1 100.00
hmac_test_sha384_vectors 437.630s 69068.306us 1 1 100.00
hmac_test_sha512_vectors 400.570s 72568.563us 1 1 100.00
hmac_test_hmac256_vectors 9.770s 1453.498us 1 1 100.00
hmac_test_hmac384_vectors 8.810s 1401.462us 1 1 100.00
hmac_test_hmac512_vectors 13.100s 2668.488us 1 1 100.00
hmac_stress_all 1346.630s 154380.189us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1346.630s 154380.189us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.690s 49.080us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.660s 41.283us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.530s 419.048us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.530s 419.048us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.710s 20.201us 1 1 100.00
hmac_csr_rw 0.870s 29.976us 1 1 100.00
hmac_csr_aliasing 2.310s 60.182us 1 1 100.00
hmac_same_csr_outstanding 0.980s 79.955us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.710s 20.201us 1 1 100.00
hmac_csr_rw 0.870s 29.976us 1 1 100.00
hmac_csr_aliasing 2.310s 60.182us 1 1 100.00
hmac_same_csr_outstanding 0.980s 79.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.980s 82.866us 1 1 100.00
hmac_tl_intg_err 1.610s 106.238us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.610s 106.238us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.190s 2890.577us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 6.060s 767.029us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 75.370s 5882.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.930s 144.416us 1 1 100.00