Simulation Results: i2c

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.72 %
  • code
  • 80.99 %
  • assert
  • 97.25 %
  • func
  • 81.92 %
  • line
  • 96.48 %
  • branch
  • 92.26 %
  • cond
  • 84.78 %
  • toggle
  • 88.00 %
  • FSM
  • 43.45 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 40.700s 3397.611us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 15.210s 905.646us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.980s 29.676us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.930s 19.534us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.200s 344.329us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.200s 295.943us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.040s 33.442us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.930s 19.534us 1 1 100.00
i2c_csr_aliasing 1.200s 295.943us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.110s 66.766us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 184.570s 9759.086us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 22.150s 2952.791us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.920s 54.627us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 74.290s 5187.570us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 22.840s 5975.050us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.220s 658.642us 1 1 100.00
i2c_host_fifo_fmt_empty 6.260s 2519.800us 1 1 100.00
i2c_host_fifo_reset_rx 2.240s 529.155us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 56.310s 3671.315us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 9.430s 829.686us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.510s 463.324us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.540s 1033.060us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 776.520s 62981.697us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.160s 883.516us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 15.050s 1191.870us 1 1 100.00
i2c_target_intr_smoke 5.050s 1459.054us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.870s 297.866us 1 1 100.00
i2c_target_fifo_reset_tx 1.620s 335.971us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 171.370s 47289.398us 1 1 100.00
i2c_target_stress_rd 15.050s 1191.870us 1 1 100.00
i2c_target_intr_stress_wr 107.770s 16742.244us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.980s 11073.636us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 34.230s 3730.716us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.570s 1505.410us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 6.960s 10090.382us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.580s 600.408us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.360s 465.078us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 22.150s 2952.791us 1 1 100.00
i2c_host_perf_precise 12.220s 594.421us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 9.430s 829.686us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.750s 195.363us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 2.000s 1651.819us 1 1 100.00
i2c_target_nack_acqfull_addr 1.990s 1773.714us 1 1 100.00
i2c_target_nack_txstretch 1.210s 209.551us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 12.700s 677.549us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.650s 493.266us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.960s 22.104us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.830s 18.041us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.240s 311.095us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.240s 311.095us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.980s 29.676us 1 1 100.00
i2c_csr_rw 0.930s 19.534us 1 1 100.00
i2c_csr_aliasing 1.200s 295.943us 1 1 100.00
i2c_same_csr_outstanding 1.380s 105.099us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.980s 29.676us 1 1 100.00
i2c_csr_rw 0.930s 19.534us 1 1 100.00
i2c_csr_aliasing 1.200s 295.943us 1 1 100.00
i2c_same_csr_outstanding 1.380s 105.099us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.610s 537.367us 1 1 100.00
i2c_sec_cm 1.140s 237.724us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.610s 537.367us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 12.170s 942.839us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.130s 21.300us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 6.490s 534.200us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_error_intr 40220362143060957370495939868313457786652862465514040726053515486337264695551 96
UVM_INFO @ 66765837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 52406507184426687477203424913874636559911889522462296583527882541676998312700 110
UVM_INFO @ 9759086262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 93285086507283390875947554773856554424246131010695987460141867937926578437211 90
UVM_INFO @ 942838566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 72858682157050579138693410115276855492864259712805535457451109144348892926900 85
UVM_INFO @ 534199981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 108512325777038193278580253694312109359755962114126549398642972666427936768183 84
UVM_INFO @ 1033059530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 20028681590346983698842751533035689709455124373652026336584875040642192566792 78
UVM_INFO @ 21299545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 111584981767819520537434457299201129244270315763642733417970773362957119268936 79
UVM_INFO @ 10090382353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead 1 test run
i2c_host_mode_toggle 52517015276132154148811222406509848770612884160816773424948073156296194518281 87
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * 1 test run
i2c_target_nack_txstretch 68385184266898868824033395185272902316455791603166788617757169881488577057807 78
UVM_INFO @ 209551426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---