Simulation Results: lc_ctrl/volatile_unlock_disabled

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.84 %
  • code
  • 84.16 %
  • assert
  • 94.41 %
  • func
  • 93.95 %
  • line
  • 97.24 %
  • branch
  • 93.70 %
  • cond
  • 78.59 %
  • toggle
  • 86.78 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.260s 759.308us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.190s 18.139us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.290s 13.673us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.680s 527.907us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.350s 49.335us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.100s 148.882us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.290s 13.673us 1 1 100.00
lc_ctrl_csr_aliasing 1.350s 49.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.550s 183.936us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.880s 847.363us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.970s 22.180us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.400s 171.582us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 10.580s 321.859us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.800s 420.341us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 10.580s 321.859us 1 1 100.00
lc_ctrl_prog_failure 2.400s 171.582us 1 1 100.00
lc_ctrl_errors 8.800s 420.341us 1 1 100.00
lc_ctrl_security_escalation 5.550s 1566.563us 1 1 100.00
lc_ctrl_jtag_state_failure 23.240s 6830.921us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.590s 179.906us 1 1 100.00
lc_ctrl_jtag_errors 22.210s 8493.640us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.980s 289.963us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.760s 2634.002us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.590s 179.906us 1 1 100.00
lc_ctrl_jtag_errors 22.210s 8493.640us 1 1 100.00
lc_ctrl_jtag_access 5.770s 1125.795us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.740s 5035.858us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.310s 58.599us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.540s 295.542us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.010s 10578.550us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.590s 528.185us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.640s 89.987us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.710s 49.567us 1 1 100.00
lc_ctrl_jtag_alert_test 1.160s 29.402us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 11.070s 3498.720us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.740s 39.715us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 98.490s 4778.761us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.890s 54.095us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.760s 103.351us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.760s 103.351us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.190s 18.139us 1 1 100.00
lc_ctrl_csr_rw 1.290s 13.673us 1 1 100.00
lc_ctrl_csr_aliasing 1.350s 49.335us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.270s 22.014us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.190s 18.139us 1 1 100.00
lc_ctrl_csr_rw 1.290s 13.673us 1 1 100.00
lc_ctrl_csr_aliasing 1.350s 49.335us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.270s 22.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.740s 234.180us 1 1 100.00
lc_ctrl_tl_intg_err 1.550s 94.485us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.550s 94.485us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.880s 847.363us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 10.580s 321.859us 1 1 100.00
lc_ctrl_sec_cm 8.740s 234.180us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 10.580s 321.859us 1 1 100.00
lc_ctrl_sec_cm 8.740s 234.180us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.580s 321.859us 1 1 100.00
lc_ctrl_sec_cm 8.740s 234.180us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.580s 321.859us 1 1 100.00
lc_ctrl_sec_cm 8.740s 234.180us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 10.580s 321.859us 1 1 100.00
lc_ctrl_sec_cm 8.740s 234.180us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.580s 321.859us 1 1 100.00
lc_ctrl_sec_cm 8.740s 234.180us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.580s 321.859us 1 1 100.00
lc_ctrl_sec_cm 8.740s 234.180us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 10.580s 321.859us 1 1 100.00
lc_ctrl_sec_cm 8.740s 234.180us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.550s 1566.563us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.550s 183.936us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.760s 2634.002us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.170s 2134.479us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.170s 2134.479us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.100s 1502.307us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.850s 351.752us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.850s 351.752us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 71.730s 6674.553us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 41753354848614519332581450041091902276335456831321469142135354261533268350398 1387
UVM_INFO @ 6674553457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---