Simulation Results: lc_ctrl/volatile_unlock_enabled

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.49 %
  • code
  • 82.91 %
  • assert
  • 94.97 %
  • func
  • 93.59 %
  • line
  • 97.13 %
  • branch
  • 93.37 %
  • cond
  • 79.13 %
  • toggle
  • 82.28 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.460s 60.010us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.880s 42.463us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.040s 15.744us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.570s 395.355us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 125.458us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.950s 53.463us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.040s 15.744us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 125.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.580s 231.949us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.400s 274.433us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.740s 23.819us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.170s 57.756us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.530s 265.809us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.080s 377.023us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.530s 265.809us 1 1 100.00
lc_ctrl_prog_failure 2.170s 57.756us 1 1 100.00
lc_ctrl_errors 8.080s 377.023us 1 1 100.00
lc_ctrl_security_escalation 5.880s 487.867us 1 1 100.00
lc_ctrl_jtag_state_failure 23.420s 1063.330us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 178.345us 1 1 100.00
lc_ctrl_jtag_errors 51.660s 5598.681us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.810s 1329.729us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.470s 1870.581us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 178.345us 1 1 100.00
lc_ctrl_jtag_errors 51.660s 5598.681us 1 1 100.00
lc_ctrl_jtag_access 6.620s 8419.299us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 25.140s 2543.819us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.120s 120.841us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.980s 40.555us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 24.040s 4792.372us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.490s 1293.544us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.080s 33.319us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.180s 389.800us 1 1 100.00
lc_ctrl_jtag_alert_test 1.040s 191.796us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 12.060s 1313.609us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.020s 23.852us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 13.780s 519.457us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.020s 163.840us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.320s 294.661us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.320s 294.661us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.880s 42.463us 1 1 100.00
lc_ctrl_csr_rw 1.040s 15.744us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 125.458us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.640s 172.088us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.880s 42.463us 1 1 100.00
lc_ctrl_csr_rw 1.040s 15.744us 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 125.458us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.640s 172.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 8.450s 1550.765us 1 1 100.00
lc_ctrl_tl_intg_err 1.360s 349.626us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.360s 349.626us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.400s 274.433us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.530s 265.809us 1 1 100.00
lc_ctrl_sec_cm 8.450s 1550.765us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.530s 265.809us 1 1 100.00
lc_ctrl_sec_cm 8.450s 1550.765us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.530s 265.809us 1 1 100.00
lc_ctrl_sec_cm 8.450s 1550.765us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.530s 265.809us 1 1 100.00
lc_ctrl_sec_cm 8.450s 1550.765us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.530s 265.809us 1 1 100.00
lc_ctrl_sec_cm 8.450s 1550.765us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.530s 265.809us 1 1 100.00
lc_ctrl_sec_cm 8.450s 1550.765us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.530s 265.809us 1 1 100.00
lc_ctrl_sec_cm 8.450s 1550.765us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.530s 265.809us 1 1 100.00
lc_ctrl_sec_cm 8.450s 1550.765us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.880s 487.867us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.580s 231.949us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.470s 1870.581us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.840s 331.303us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.840s 331.303us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 10.700s 740.525us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.130s 2601.219us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.130s 2601.219us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 17.380s 2848.370us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 9586828815878082056451847415910918176847879494563238125965652608292494328800 3455
UVM_INFO @ 2848370311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---