Simulation Results: otbn

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.14 %
  • code
  • 81.85 %
  • assert
  • 90.25 %
  • func
  • 98.31 %
  • block
  • 97.74 %
  • line
  • 97.94 %
  • branch
  • 81.85 %
  • toggle
  • 81.41 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 13.000s 134.990us 1 1 100.00
single_binary 1 1 100.00
otbn_single 8.000s 47.493us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 26.000s 37.474us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 25.000s 36.007us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 27.000s 73.427us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 27.000s 56.910us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 31.000s 37.915us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 25.000s 36.007us 1 1 100.00
otbn_csr_aliasing 27.000s 56.910us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 69.000s 3367.419us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 21.000s 664.394us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 29.000s 357.428us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 57.000s 1297.743us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 106.000s 1254.585us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 7.000s 20.426us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 26.000s 20.184us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.155us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 38.641us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 28.000s 19.495us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 18.000s 58.751us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 255.918us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 255.918us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 26.000s 37.474us 1 1 100.00
otbn_csr_rw 25.000s 36.007us 1 1 100.00
otbn_csr_aliasing 27.000s 56.910us 1 1 100.00
otbn_same_csr_outstanding 4.000s 15.346us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 26.000s 37.474us 1 1 100.00
otbn_csr_rw 25.000s 36.007us 1 1 100.00
otbn_csr_aliasing 27.000s 56.910us 1 1 100.00
otbn_same_csr_outstanding 4.000s 15.346us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 21.000s 57.231us 1 1 100.00
otbn_dmem_err 27.000s 59.909us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 45.000s 82.898us 1 1 100.00
otbn_controller_ispr_rdata_err 31.000s 224.096us 1 1 100.00
otbn_mac_bignum_acc_err 19.000s 54.935us 1 1 100.00
otbn_urnd_err 10.000s 201.215us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 23.000s 23.639us 1 1 100.00
otbn_mem_gnt_acc_err 0 1 0.00
otbn_mem_gnt_acc_err 136.000s 10004.376us 0 1 0.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 58.039us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
otbn_tl_intg_err 19.000s 515.609us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 4.000s 2.952us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 13.000s 134.990us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 27.000s 59.909us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 21.000s 57.231us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 19.000s 515.609us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 26.000s 20.184us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 21.000s 57.231us 1 1 100.00
otbn_dmem_err 27.000s 59.909us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.155us 1 1 100.00
otbn_illegal_mem_acc 23.000s 23.639us 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 8.000s 47.493us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 21.000s 57.231us 1 1 100.00
otbn_dmem_err 27.000s 59.909us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.155us 1 1 100.00
otbn_illegal_mem_acc 23.000s 23.639us 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 26.000s 20.184us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 21.000s 57.231us 1 1 100.00
otbn_dmem_err 27.000s 59.909us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.155us 1 1 100.00
otbn_illegal_mem_acc 23.000s 23.639us 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 8.000s 47.493us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 27.000s 25.062us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 9.000s 20.517us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 58.000s 1764.849us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 58.000s 1764.849us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 37.526us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 64.347us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 12.000s 102.975us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 12.000s 102.975us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 15.000s 47.802us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 47.493us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 8.000s 47.493us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 8.000s 47.493us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 106.000s 1254.585us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 8.000s 47.493us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 8.000s 47.493us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 231.792us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 8.000s 47.493us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 334.000s 5861.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 102.000s 1731.891us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 20.731us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 68200236796171903299928003366368640344894761377110242320495531784664450472084 299
UVM_INFO @ 1731890572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_mem_gnt_acc_err_vseq.sv:41) [otbn_mem_gnt_acc_err_vseq] timeout occurred! 1 test run
otbn_mem_gnt_acc_err 74150536952833035901992051237409257077141701938006007563952091707809165568455 112
UVM_INFO @ 10004376050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 27952200417794569133610340050316968868289463813515771032838227938117844100777 86
UVM_INFO @ 2951770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---