Simulation Results: otp_ctrl

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.33 %
  • code
  • 76.37 %
  • assert
  • 94.76 %
  • func
  • 69.86 %
  • line
  • 88.52 %
  • branch
  • 83.26 %
  • cond
  • 90.21 %
  • toggle
  • 78.19 %
  • FSM
  • 41.67 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.610s 102.953us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.080s 2553.791us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.880s 150.512us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.560s 79.561us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.190s 105.886us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.980s 377.526us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.950s 158.244us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.560s 79.561us 1 1 100.00
otp_ctrl_csr_aliasing 4.980s 377.526us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.490s 42.215us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.540s 139.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 12.900s 1683.298us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.620s 205.365us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 26.850s 5260.337us 1 1 100.00
otp_ctrl_check_fail 11.190s 2299.836us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.690s 1110.228us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 13.290s 1019.172us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 29.990s 3520.259us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 13.570s 2417.529us 1 1 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 8.940s 682.759us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 7.670s 391.925us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 7.780s 4886.801us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 11.690s 8847.325us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.230s 39.479us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.530s 115.299us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.870s 177.767us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.870s 177.767us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.880s 150.512us 1 1 100.00
otp_ctrl_csr_rw 1.560s 79.561us 1 1 100.00
otp_ctrl_csr_aliasing 4.980s 377.526us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.790s 216.040us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.880s 150.512us 1 1 100.00
otp_ctrl_csr_rw 1.560s 79.561us 1 1 100.00
otp_ctrl_csr_aliasing 4.980s 377.526us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.790s 216.040us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
otp_ctrl_tl_intg_err 13.110s 2572.245us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 13.110s 2572.245us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.080s 2553.791us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.080s 2553.791us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
otp_ctrl_macro_errs 7.670s 391.925us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
otp_ctrl_macro_errs 7.670s 391.925us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 1.670s 60.397us 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.620s 205.365us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 11.190s 2299.836us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 13.290s 1019.172us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 13.290s 1019.172us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 13.290s 1019.172us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 13.290s 1019.172us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 13.290s 1019.172us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.080s 2553.791us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 13.290s 1019.172us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.080s 2553.791us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.430s 23441.168us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.690s 1110.228us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.080s 2553.791us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.080s 2553.791us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 7.670s 391.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 18.430s 9129.195us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 39.990s 1471.473us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 6354652102930867883671189070699950186614227561578358244583779168203998892652 7492
UVM_INFO @ 2299836082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1831) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 49773168948746574955118760821017004016034008184127669509805541579577136104889 25398
UVM_INFO @ 1471473171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---