Simulation Results: pwrmgr

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.47 %
  • code
  • 95.70 %
  • assert
  • 98.69 %
  • func
  • 98.02 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.90 %
  • toggle
  • 91.15 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.610s 31.751us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.760s 52.482us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.630s 22.136us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.660s 397.569us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.280s 70.370us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.850s 93.196us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.630s 22.136us 1 1 100.00
pwrmgr_csr_aliasing 1.280s 70.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.640s 27.716us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.640s 27.716us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 1.310s 210.926us 1 1 100.00
pwrmgr_lowpower_invalid 0.720s 111.893us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.680s 23.921us 1 1 100.00
pwrmgr_reset_invalid 0.770s 98.921us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.680s 23.921us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.680s 60.735us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.830s 204.605us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.880s 96.737us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 4.790s 12050.903us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.630s 95.011us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.760s 131.586us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.760s 131.586us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.760s 52.482us 1 1 100.00
pwrmgr_csr_rw 0.630s 22.136us 1 1 100.00
pwrmgr_csr_aliasing 1.280s 70.370us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 32.684us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.760s 52.482us 1 1 100.00
pwrmgr_csr_rw 0.630s 22.136us 1 1 100.00
pwrmgr_csr_aliasing 1.280s 70.370us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 32.684us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.480s 256.734us 1 1 100.00
pwrmgr_sec_cm 1.180s 342.374us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.180s 342.374us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.180s 342.374us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.480s 256.734us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.470s 961.966us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.680s 60.735us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.260s 1402.505us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.820s 74.288us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.630s 32.344us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.180s 342.374us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.180s 342.374us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.180s 342.374us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.800s 73.304us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.620s 58.083us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.720s 470.515us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 22.136us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 22.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.710s 1251.269us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.710s 895.750us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 99123630947286559195739024570229482446189064525225960209833644961512845534089 79
UVM_ERROR @ 1251268660 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 1251268660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 75135285989587045294933162914782517731763915693864184350244655872680816403033 969
UVM_INFO @ 12050902857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---