Simulation Results: rom_ctrl/32kb

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.88 %
  • code
  • 98.50 %
  • assert
  • 96.81 %
  • func
  • 98.33 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.51 %
  • toggle
  • 94.87 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.960s 173.479us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.510s 373.186us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.160s 5502.717us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.120s 792.930us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.900s 283.192us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.070s 587.664us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.160s 5502.717us 1 1 100.00
rom_ctrl_csr_aliasing 3.900s 283.192us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.430s 1168.761us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.510s 534.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.770s 239.815us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.790s 1159.872us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.430s 2810.194us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.030s 866.124us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.020s 292.532us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.020s 292.532us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.510s 373.186us 1 1 100.00
rom_ctrl_csr_rw 4.160s 5502.717us 1 1 100.00
rom_ctrl_csr_aliasing 3.900s 283.192us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.860s 556.658us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.510s 373.186us 1 1 100.00
rom_ctrl_csr_rw 4.160s 5502.717us 1 1 100.00
rom_ctrl_csr_aliasing 3.900s 283.192us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.860s 556.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.290s 18258.667us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.370s 1587.838us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 105.100s 387.609us 1 1 100.00
rom_ctrl_tl_intg_err 43.460s 910.932us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 105.100s 387.609us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 105.100s 387.609us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.290s 18258.667us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.290s 18258.667us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.290s 18258.667us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.290s 18258.667us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.290s 18258.667us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.100s 387.609us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 105.100s 387.609us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.960s 173.479us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.960s 173.479us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.960s 173.479us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 43.460s 910.932us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.290s 18258.667us 1 1 100.00
rom_ctrl_kmac_err_chk 7.430s 2810.194us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.290s 18258.667us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.290s 18258.667us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.290s 18258.667us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 19.370s 1587.838us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 105.100s 387.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 103.070s 4111.615us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 83693332115108359983987543386536630285289227318239847485368931627124943611789 79
UVM_INFO @ 239815110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---