Simulation Results: rom_ctrl/64kb

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.82 %
  • code
  • 95.42 %
  • assert
  • 96.81 %
  • func
  • 95.23 %
  • line
  • 99.33 %
  • branch
  • 98.91 %
  • cond
  • 97.33 %
  • toggle
  • 94.87 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.570s 309.771us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.860s 217.248us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.700s 1075.720us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.820s 726.331us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.160s 698.231us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.060s 810.840us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.700s 1075.720us 1 1 100.00
rom_ctrl_csr_aliasing 6.160s 698.231us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.440s 2290.132us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.080s 298.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 7.400s 251.203us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 28.970s 29571.340us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.620s 5549.229us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.110s 215.845us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.020s 205.460us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.020s 205.460us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.860s 217.248us 1 1 100.00
rom_ctrl_csr_rw 6.700s 1075.720us 1 1 100.00
rom_ctrl_csr_aliasing 6.160s 698.231us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.250s 377.082us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.860s 217.248us 1 1 100.00
rom_ctrl_csr_rw 6.700s 1075.720us 1 1 100.00
rom_ctrl_csr_aliasing 6.160s 698.231us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.250s 377.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.630s 45718.027us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.720s 2203.777us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 457.820s 673.205us 1 1 100.00
rom_ctrl_tl_intg_err 53.660s 310.068us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 457.820s 673.205us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 457.820s 673.205us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.630s 45718.027us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.630s 45718.027us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.630s 45718.027us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.630s 45718.027us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.630s 45718.027us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 457.820s 673.205us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 457.820s 673.205us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.570s 309.771us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.570s 309.771us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.570s 309.771us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 53.660s 310.068us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.630s 45718.027us 1 1 100.00
rom_ctrl_kmac_err_chk 13.620s 5549.229us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.630s 45718.027us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.630s 45718.027us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.630s 45718.027us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.720s 2203.777us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 457.820s 673.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 172.100s 5353.477us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 87912518533830279913914984487054306615062316318999443589477545181790168729169 79
UVM_INFO @ 251202702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---