Simulation Results: rstmgr

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.16 %
  • code
  • 99.30 %
  • assert
  • 98.66 %
  • func
  • 96.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.54 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.160s 261.694us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.010s 97.996us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.900s 80.871us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.960s 2859.212us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.040s 441.708us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.940s 144.661us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.900s 80.871us 1 1 100.00
rstmgr_csr_aliasing 2.040s 441.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.010s 196.150us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.440s 673.155us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.580s 311.900us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.550s 1791.456us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.550s 1791.456us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.550s 1791.456us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.550s 1791.456us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 9.510s 3093.341us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.700s 64.988us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.900s 171.992us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.900s 171.992us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.010s 97.996us 1 1 100.00
rstmgr_csr_rw 0.900s 80.871us 1 1 100.00
rstmgr_csr_aliasing 2.040s 441.708us 1 1 100.00
rstmgr_same_csr_outstanding 1.050s 133.065us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.010s 97.996us 1 1 100.00
rstmgr_csr_rw 0.900s 80.871us 1 1 100.00
rstmgr_csr_aliasing 2.040s 441.708us 1 1 100.00
rstmgr_same_csr_outstanding 1.050s 133.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 21.330s 16804.675us 1 1 100.00
rstmgr_tl_intg_err 1.750s 515.276us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 21.330s 16804.675us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 21.330s 16804.675us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.750s 515.276us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.890s 109.616us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.500s 1407.424us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.190s 302.249us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 21.330s 16804.675us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.900s 80.871us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.900s 80.871us 1 1 100.00