Simulation Results: rv_timer

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.52 %
  • code
  • 94.66 %
  • assert
  • 98.73 %
  • func
  • 96.18 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.610s 21.832us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.680s 48.839us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.600s 38.875us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.240s 94.332us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.720s 95.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.800s 54.840us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.600s 38.875us 1 1 100.00
rv_timer_csr_aliasing 0.720s 95.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.780s 57.114us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.610s 2751.549us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 480.700s 538290.752us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 480.700s 538290.752us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.640s 4975.570us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 28.615us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.610s 46.585us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.680s 186.471us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.680s 186.471us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.680s 48.839us 1 1 100.00
rv_timer_csr_rw 0.600s 38.875us 1 1 100.00
rv_timer_csr_aliasing 0.720s 95.000us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 47.946us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.680s 48.839us 1 1 100.00
rv_timer_csr_rw 0.600s 38.875us 1 1 100.00
rv_timer_csr_aliasing 0.720s 95.000us 1 1 100.00
rv_timer_same_csr_outstanding 0.670s 47.946us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.730s 453.115us 1 1 100.00
rv_timer_tl_intg_err 1.160s 487.149us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.160s 487.149us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.640s 168.785us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.980s 413.682us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 30.630s 3782.906us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 13108812161823304199631665633361678974487041447526990134564709098758034431171 75
UVM_INFO @ 168784657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 91866464463944165151198294506253438188528713295330182086567160173982580918627 75
UVM_INFO @ 57114220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 98570197067962997130319696451721414005556070704713553921517623442921263879231 75
UVM_INFO @ 413682116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---