Simulation Results: spi_device/1r1w

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.94 %
  • code
  • 91.27 %
  • assert
  • 95.40 %
  • func
  • 68.15 %
  • line
  • 98.83 %
  • branch
  • 98.09 %
  • cond
  • 95.78 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 269.310s 149425.265us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.010s 20.088us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.080s 65.115us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.690s 5707.840us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 10.370s 1156.891us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.750s 1049.460us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.080s 65.115us 1 1 100.00
spi_device_csr_aliasing 10.370s 1156.891us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.630s 35.105us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 0.940s 18.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.850s 23.515us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.760s 1.578us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.820s 3.963us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.280s 301.002us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.280s 301.002us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.490s 2090.139us 1 1 100.00
spi_device_tpm_sts_read 0.760s 80.459us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 5.990s 13086.090us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.980s 185.454us 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.420s 697.100us 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.420s 697.100us 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 6.580s 929.924us 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 6.580s 929.924us 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 6.580s 929.924us 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 6.580s 929.924us 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 6.580s 929.924us 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 6.810s 2991.470us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.740s 80.514us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.740s 80.514us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.740s 80.514us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 25.450s 10698.802us 1 1 100.00
spi_device_read_buffer_direct 5.500s 1606.715us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.740s 80.514us 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 3.810s 2788.292us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.370s 3652.995us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.370s 3652.995us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 23.320s 5427.393us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 269.310s 149425.265us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 428.590s 334536.749us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 19.990s 2597.623us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.840s 13.664us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.700s 55.472us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.420s 31.563us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.420s 31.563us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.010s 20.088us 1 1 100.00
spi_device_csr_rw 2.080s 65.115us 1 1 100.00
spi_device_csr_aliasing 10.370s 1156.891us 1 1 100.00
spi_device_same_csr_outstanding 1.360s 33.619us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.010s 20.088us 1 1 100.00
spi_device_csr_rw 2.080s 65.115us 1 1 100.00
spi_device_csr_aliasing 10.370s 1156.891us 1 1 100.00
spi_device_same_csr_outstanding 1.360s 33.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.020s 37.758us 1 1 100.00
spi_device_tl_intg_err 10.930s 303.559us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 10.930s 303.559us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 68410417897483657949266603906464138502282338967080814698979065711908839449498 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 957875 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 957875 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[993])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 16690146117469321290211742670397562055534321313761428302073053761500352249213 76
UVM_ERROR @ 1628754 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3a4 [1110100100] vs 0x0 [0])
UVM_ERROR @ 1640754 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x37 [110111] vs 0x0 [0])
UVM_ERROR @ 1663754 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x347 [1101000111] vs 0x0 [0])
UVM_ERROR @ 1729754 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x354 [1101010100] vs 0x0 [0])