Simulation Results: spi_host

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.68 %
  • code
  • 91.25 %
  • assert
  • 94.71 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 72.90 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 7.000s 1738.839us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 61.566us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 49.476us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 250.593us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 32.442us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 41.037us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 49.476us 1 1 100.00
spi_host_csr_aliasing 2.000s 32.442us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 21.435us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 82.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 25.131us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 262.725us 1 1 100.00
spi_host_error_cmd 2.000s 54.835us 1 1 100.00
spi_host_event 11.000s 3709.405us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 91.829us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 91.829us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 91.829us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 65.000s 7629.930us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 14.000s 602.268us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 24.151us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 91.829us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 91.829us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 7.000s 1738.839us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 7.000s 1738.839us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 196.683us 1 1 100.00
spien 1 1 100.00
spi_host_spien 9.000s 1231.224us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 41.000s 4719.662us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 1.000s 324.591us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 262.725us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 23.482us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 43.616us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 80.082us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 80.082us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 61.566us 1 1 100.00
spi_host_csr_rw 1.000s 49.476us 1 1 100.00
spi_host_csr_aliasing 2.000s 32.442us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 55.199us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 61.566us 1 1 100.00
spi_host_csr_rw 1.000s 49.476us 1 1 100.00
spi_host_csr_aliasing 2.000s 32.442us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 55.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 3.000s 108.239us 1 1 100.00
spi_host_sec_cm 1.000s 121.311us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 3.000s 108.239us 1 1 100.00