Simulation Results: sram_ctrl/main

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.86 %
  • code
  • 95.69 %
  • assert
  • 97.28 %
  • func
  • 94.60 %
  • block
  • 96.03 %
  • line
  • 96.75 %
  • branch
  • 94.17 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 383.351us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 30.217us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.099us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 848.895us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.251us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 594.093us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 11.099us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.251us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 115.000s 13261.522us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 52.000s 6594.857us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 13.000s 11819.253us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 136.000s 29081.906us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 159.000s 174870.457us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 26.000s 5824.748us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 11.000s 12253.296us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 13.000s 2910.937us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 2081.349us 1 1 100.00
sram_ctrl_partial_access_b2b 293.000s 136891.094us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 3.000s 682.964us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 2753.806us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 4380.507us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 485.039us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1401.164us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 79.000s 26557.293us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 31.415us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 100.072us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 100.072us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 30.217us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.099us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.251us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 27.991us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 30.217us 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.099us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 20.251us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 27.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 10.000s 3981.228us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1515.817us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 229.536us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1515.817us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 229.536us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 485.039us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 485.039us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 11.099us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 13.000s 2910.937us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 2910.937us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 2910.937us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 11.000s 12253.296us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 2789.678us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 10.000s 3981.228us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 3949.591us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 383.351us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 383.351us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 13.000s 2910.937us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1515.817us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 11.000s 12253.296us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1515.817us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1515.817us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 383.351us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1515.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.000s 2510.681us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 3507687544134045815238450258787208378688283925980367673391989711816394109268 86
UVM_INFO @ 682963656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 29184862076126042610963228274892945015780706762334895567699843325148410457344 86
UVM_INFO @ 2753805527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 31187608631403993451087929481428821679904378476521030362242593904369838766359 86
UVM_INFO @ 4380506508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---