Simulation Results: sysrst_ctrl

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.68 %
  • code
  • 93.32 %
  • assert
  • 94.64 %
  • func
  • 66.08 %
  • line
  • 97.64 %
  • branch
  • 97.59 %
  • cond
  • 95.10 %
  • toggle
  • 100.00 %
  • FSM
  • 76.28 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 3.740s 2108.581us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 3.100s 2468.903us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.630s 2444.078us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.280s 2245.585us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.490s 6041.750us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.780s 2031.678us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 23.060s 76955.132us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 7.450s 2742.328us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.300s 2351.427us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.780s 2031.678us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.450s 2742.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 67.360s 141931.586us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 129.330s 170109.663us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 27.860s 61990.780us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.800s 2916.002us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.750s 2513.050us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.210s 2233.222us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.100s 3325.302us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 4.920s 2612.156us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.990s 10626.737us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 20.820s 38110.468us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 29.550s 17951.721us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.500s 2028.169us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.880s 2013.511us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 6.720s 2021.611us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 6.720s 2021.611us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.490s 6041.750us 1 1 100.00
sysrst_ctrl_csr_rw 3.780s 2031.678us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.450s 2742.328us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.310s 4500.649us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.490s 6041.750us 1 1 100.00
sysrst_ctrl_csr_rw 3.780s 2031.678us 1 1 100.00
sysrst_ctrl_csr_aliasing 7.450s 2742.328us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.310s 4500.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 17.510s 42486.011us 1 1 100.00
sysrst_ctrl_tl_intg_err 18.500s 42899.781us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 18.500s 42899.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 10.780s 9602.436us 1 1 100.00