Simulation Results: uart

 
22/07/2026 15:30:29 DVSim: v1.50.0 sha: a22166c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.04 %
  • code
  • 91.51 %
  • assert
  • 98.27 %
  • func
  • 50.33 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 95.22 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 13.760s 6066.576us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 36.582us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.660s 21.537us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 313.275us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.820s 113.751us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.760s 42.362us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.660s 21.537us 1 1 100.00
uart_csr_aliasing 0.820s 113.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 12.650s 124672.190us 1 1 100.00
parity 2 2 100.00
uart_smoke 13.760s 6066.576us 1 1 100.00
uart_tx_rx 12.650s 124672.190us 1 1 100.00
parity_error 2 2 100.00
uart_intr 24.590s 57307.309us 1 1 100.00
uart_rx_parity_err 113.210s 154471.106us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 12.650s 124672.190us 1 1 100.00
uart_intr 24.590s 57307.309us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 38.880s 427793.241us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 24.730s 128865.123us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 19.210s 13695.467us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 24.590s 57307.309us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 24.590s 57307.309us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 24.590s 57307.309us 1 1 100.00
perf 1 1 100.00
uart_perf 541.560s 22695.082us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 0.790s 206.556us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 0.790s 206.556us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 4.130s 16920.982us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.260s 4588.503us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.570s 1230.445us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 21.370s 5398.589us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 216.510s 119835.474us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 53.570s 65956.509us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.780s 19.256us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.710s 19.847us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.080s 106.168us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.080s 106.168us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 36.582us 1 1 100.00
uart_csr_rw 0.660s 21.537us 1 1 100.00
uart_csr_aliasing 0.820s 113.751us 1 1 100.00
uart_same_csr_outstanding 0.690s 19.841us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 36.582us 1 1 100.00
uart_csr_rw 0.660s 21.537us 1 1 100.00
uart_csr_aliasing 0.820s 113.751us 1 1 100.00
uart_same_csr_outstanding 0.690s 19.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.780s 165.498us 1 1 100.00
uart_tl_intg_err 1.100s 76.826us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.100s 76.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 24.570s 9908.097us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_stress_all 12711979389275109971117791478439406393292256688171685785404871711260594858328 193
UVM_ERROR @ 65627050710 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 65627061127 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 65695667489 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4, clk_pulses: 0
UVM_ERROR @ 65695688323 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty