Simulation Results: adc_ctrl

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.79 %
  • code
  • 93.24 %
  • assert
  • 92.54 %
  • func
  • 11.59 %
  • line
  • 98.74 %
  • branch
  • 97.22 %
  • cond
  • 86.68 %
  • toggle
  • 99.76 %
  • FSM
  • 83.78 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.410s 5832.788us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.880s 999.272us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.940s 563.882us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 12.460s 46616.243us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.740s 984.354us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.980s 422.271us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.940s 563.882us 1 1 100.00
adc_ctrl_csr_aliasing 2.740s 984.354us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.000s 510.675us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.150s 412.665us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.830s 465.919us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.830s 407.832us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.790s 396.920us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.890s 486.727us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.800s 432.222us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.030s 341.831us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.040s 3971.479us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 10.390s 32350.941us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 26.640s 74030.434us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 4.950s 6774.170us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.690s 351.468us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.800s 448.950us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.660s 458.278us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.660s 458.278us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.880s 999.272us 1 1 100.00
adc_ctrl_csr_rw 0.940s 563.882us 1 1 100.00
adc_ctrl_csr_aliasing 2.740s 984.354us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.290s 2741.559us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.880s 999.272us 1 1 100.00
adc_ctrl_csr_rw 0.940s 563.882us 1 1 100.00
adc_ctrl_csr_aliasing 2.740s 984.354us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.290s 2741.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 11.670s 7936.426us 1 1 100.00
adc_ctrl_tl_intg_err 4.490s 4473.371us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 4.490s 4473.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 2.730s 1362.358us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 43148992653455939685361845664948113062354280520129742168224358833119883702769 386
UVM_INFO @ 510675122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 99994193853686756340218379294217961699717956236856161666392472948215331204151 386
UVM_INFO @ 412665485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 18513006175468776482263084845571552954089280217407154595431611178469166862218 386
UVM_INFO @ 465918780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 32604391936200548430254760324709897021632466768977889786927602168952819031924 386
UVM_INFO @ 407832313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 88910861741154777138753269748649562409995042487703391472045299825799959475490 386
UVM_INFO @ 396920198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 88571141295250364097920295828556531466024960103612294846154080926662027021139 386
UVM_INFO @ 486727388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 47073484643211085948023292638241404398280963785857124824777854340925070852227 386
UVM_INFO @ 341831431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 72271730887955402578177813671922562549539910192907143453004376337663997297644 386
UVM_INFO @ 432221900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 8400912489481274715195664636846628821925572176842292926375899014184630292175 410
UVM_INFO @ 1362357958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 37178847381721378648024007400388642363462383399187315917547115695522018469616 389
UVM_INFO @ 6774170020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---