Simulation Results: aes/masked

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.56 %
  • code
  • 94.16 %
  • assert
  • 98.23 %
  • func
  • 76.29 %
  • block
  • 94.28 %
  • line
  • 95.88 %
  • branch
  • 87.20 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 72.712us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 105.148us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 90.087us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 61.826us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 154.984us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 483.785us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 191.139us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 61.826us 1 1 100.00
aes_csr_aliasing 3.000s 483.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 105.148us 1 1 100.00
aes_config_error 3.000s 614.824us 1 1 100.00
aes_stress 3.000s 593.415us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 105.148us 1 1 100.00
aes_config_error 3.000s 614.824us 1 1 100.00
aes_stress 3.000s 593.415us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 593.415us 1 1 100.00
aes_b2b 17.000s 411.361us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 593.415us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 105.148us 1 1 100.00
aes_config_error 3.000s 614.824us 1 1 100.00
aes_stress 3.000s 593.415us 1 1 100.00
aes_alert_reset 5.000s 275.220us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 125.050us 1 1 100.00
aes_config_error 3.000s 614.824us 1 1 100.00
aes_alert_reset 5.000s 275.220us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 39.000s 3559.554us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 42.000s 7497.285us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 275.220us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 593.415us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 593.415us 1 1 100.00
aes_sideload 4.000s 166.994us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 127.337us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.067s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 54.275us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 1004.135us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 1004.135us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 90.087us 1 1 100.00
aes_csr_rw 2.000s 61.826us 1 1 100.00
aes_csr_aliasing 3.000s 483.785us 1 1 100.00
aes_same_csr_outstanding 2.000s 63.732us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 90.087us 1 1 100.00
aes_csr_rw 2.000s 61.826us 1 1 100.00
aes_csr_aliasing 3.000s 483.785us 1 1 100.00
aes_same_csr_outstanding 2.000s 63.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 107.980us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 4.000s 158.313us 0 1 0.00
aes_control_fi 2.000s 64.972us 1 1 100.00
aes_cipher_fi 3.000s 49.888us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 79.535us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 79.535us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 79.535us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 79.535us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 134.949us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1901.162us 1 1 100.00
aes_tl_intg_err 2.000s 621.320us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 621.320us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 275.220us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 79.535us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 79.535us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 105.148us 1 1 100.00
aes_stress 3.000s 593.415us 1 1 100.00
aes_alert_reset 5.000s 275.220us 1 1 100.00
aes_core_fi 2.000s 64.452us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 614.824us 1 1 100.00
aes_stress 3.000s 593.415us 1 1 100.00
aes_core_fi 2.000s 64.452us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 79.535us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 66.561us 1 1 100.00
aes_stress 3.000s 593.415us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 593.415us 1 1 100.00
aes_sideload 4.000s 166.994us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.561us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 66.561us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 66.561us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 66.561us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 66.561us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 593.415us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 593.415us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 158.313us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 158.313us 0 1 0.00
aes_control_fi 2.000s 64.972us 1 1 100.00
aes_cipher_fi 3.000s 49.888us 1 1 100.00
aes_ctr_fi 2.000s 80.590us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 158.313us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 158.313us 0 1 0.00
aes_control_fi 2.000s 64.972us 1 1 100.00
aes_cipher_fi 3.000s 49.888us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 49.888us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 158.313us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 158.313us 0 1 0.00
aes_control_fi 2.000s 64.972us 1 1 100.00
aes_ctr_fi 2.000s 80.590us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 158.313us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 158.313us 0 1 0.00
aes_control_fi 2.000s 64.972us 1 1 100.00
aes_cipher_fi 3.000s 49.888us 1 1 100.00
aes_ctr_fi 2.000s 80.590us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 275.220us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 158.313us 0 1 0.00
aes_control_fi 2.000s 64.972us 1 1 100.00
aes_cipher_fi 3.000s 49.888us 1 1 100.00
aes_ctr_fi 2.000s 80.590us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 158.313us 0 1 0.00
aes_control_fi 2.000s 64.972us 1 1 100.00
aes_cipher_fi 3.000s 49.888us 1 1 100.00
aes_ctr_fi 2.000s 80.590us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 158.313us 0 1 0.00
aes_control_fi 2.000s 64.972us 1 1 100.00
aes_ctr_fi 2.000s 80.590us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 158.313us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 158.313us 0 1 0.00
aes_control_fi 2.000s 64.972us 1 1 100.00
aes_cipher_fi 3.000s 49.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 7.160us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 21609212233221701839053666670834379688537848513884381857009409735577656166679 14821
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_stress_all 24369437747795098046807190606707464325457398249529155644392736602887380255548 None
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 60461918318460385752222983651556794859094403409571167041242273153933953599713 135
UVM_INFO @ 7160276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---