Simulation Results: aes/unmasked

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.49 %
  • code
  • 89.67 %
  • assert
  • 97.73 %
  • func
  • 72.08 %
  • block
  • 89.60 %
  • line
  • 91.90 %
  • branch
  • 79.91 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 80.561us 1 1 100.00
smoke 1 1 100.00
aes_smoke 1.000s 63.973us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 61.424us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 64.104us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 1429.372us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 628.406us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 57.022us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 64.104us 1 1 100.00
aes_csr_aliasing 3.000s 628.406us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 1.000s 63.973us 1 1 100.00
aes_config_error 2.000s 234.926us 1 1 100.00
aes_stress 2.000s 88.047us 1 1 100.00
key_length 3 3 100.00
aes_smoke 1.000s 63.973us 1 1 100.00
aes_config_error 2.000s 234.926us 1 1 100.00
aes_stress 2.000s 88.047us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 88.047us 1 1 100.00
aes_b2b 3.000s 106.182us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 88.047us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 1.000s 63.973us 1 1 100.00
aes_config_error 2.000s 234.926us 1 1 100.00
aes_stress 2.000s 88.047us 1 1 100.00
aes_alert_reset 2.000s 78.429us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 202.188us 1 1 100.00
aes_config_error 2.000s 234.926us 1 1 100.00
aes_alert_reset 2.000s 78.429us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 136.187us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 255.584us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 78.429us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 88.047us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 88.047us 1 1 100.00
aes_sideload 2.000s 61.409us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 72.143us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 13.000s 2756.089us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 105.583us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 584.217us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 584.217us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 61.424us 1 1 100.00
aes_csr_rw 1.000s 64.104us 1 1 100.00
aes_csr_aliasing 3.000s 628.406us 1 1 100.00
aes_same_csr_outstanding 2.000s 85.315us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 61.424us 1 1 100.00
aes_csr_rw 1.000s 64.104us 1 1 100.00
aes_csr_aliasing 3.000s 628.406us 1 1 100.00
aes_same_csr_outstanding 2.000s 85.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 827.600us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 83.108us 0 1 0.00
aes_control_fi 2.000s 68.313us 1 1 100.00
aes_cipher_fi 2.000s 54.191us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 7.000s 159.499us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 7.000s 159.499us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 7.000s 159.499us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 7.000s 159.499us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 100.217us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 831.468us 1 1 100.00
aes_tl_intg_err 2.000s 954.104us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 954.104us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 78.429us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 7.000s 159.499us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 7.000s 159.499us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 1.000s 63.973us 1 1 100.00
aes_stress 2.000s 88.047us 1 1 100.00
aes_alert_reset 2.000s 78.429us 1 1 100.00
aes_core_fi 3.000s 79.988us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 234.926us 1 1 100.00
aes_stress 2.000s 88.047us 1 1 100.00
aes_core_fi 3.000s 79.988us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 7.000s 159.499us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 72.963us 1 1 100.00
aes_stress 2.000s 88.047us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 88.047us 1 1 100.00
aes_sideload 2.000s 61.409us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 72.963us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 72.963us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 72.963us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 72.963us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 72.963us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 88.047us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 88.047us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 83.108us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 83.108us 0 1 0.00
aes_control_fi 2.000s 68.313us 1 1 100.00
aes_cipher_fi 2.000s 54.191us 1 1 100.00
aes_ctr_fi 1.000s 82.719us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 83.108us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 83.108us 0 1 0.00
aes_control_fi 2.000s 68.313us 1 1 100.00
aes_cipher_fi 2.000s 54.191us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 54.191us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 83.108us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 83.108us 0 1 0.00
aes_control_fi 2.000s 68.313us 1 1 100.00
aes_ctr_fi 1.000s 82.719us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 83.108us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 83.108us 0 1 0.00
aes_control_fi 2.000s 68.313us 1 1 100.00
aes_cipher_fi 2.000s 54.191us 1 1 100.00
aes_ctr_fi 1.000s 82.719us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 78.429us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 83.108us 0 1 0.00
aes_control_fi 2.000s 68.313us 1 1 100.00
aes_cipher_fi 2.000s 54.191us 1 1 100.00
aes_ctr_fi 1.000s 82.719us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 83.108us 0 1 0.00
aes_control_fi 2.000s 68.313us 1 1 100.00
aes_cipher_fi 2.000s 54.191us 1 1 100.00
aes_ctr_fi 1.000s 82.719us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 83.108us 0 1 0.00
aes_control_fi 2.000s 68.313us 1 1 100.00
aes_ctr_fi 1.000s 82.719us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 83.108us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 83.108us 0 1 0.00
aes_control_fi 2.000s 68.313us 1 1 100.00
aes_cipher_fi 2.000s 54.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 456.248us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 83531791361460286700156699469829861357905320758962036426925570681566013850532 3352
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 1
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 99562099387644209145277917233116755058189265310787766195882179946029414757088 446
UVM_INFO @ 456248223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---