Simulation Results: chip

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.82 %
  • code
  • 81.91 %
  • assert
  • 97.37 %
  • func
  • 54.19 %
  • line
  • 94.44 %
  • branch
  • 94.19 %
  • cond
  • 89.85 %
  • toggle
  • 73.94 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
74.73%
V2S
100.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 190.970s 4210.757us 1 1 100.00
chip_sw_example_rom 91.740s 3540.496us 1 1 100.00
chip_sw_example_manufacturer 184.140s 3953.186us 1 1 100.00
chip_sw_example_concurrency 222.860s 4319.249us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 303.140s 8217.986us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 418.450s 5578.651us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 661.260s 8978.217us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3139.510s 27585.234us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 359.720s 7665.714us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3139.510s 27585.234us 1 1 100.00
chip_csr_rw 418.450s 5578.651us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.460s 200.018us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 278.680s 4191.319us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 278.680s 4191.319us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 278.680s 4191.319us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 353.060s 4463.825us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 353.060s 4463.825us 1 1 100.00
chip_sw_uart_tx_rx_idx1 463.410s 5089.811us 1 1 100.00
chip_sw_uart_tx_rx_idx2 410.880s 5428.564us 1 1 100.00
chip_sw_uart_tx_rx_idx3 419.300s 4724.376us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 442.100s 5040.353us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1110.000s 8917.270us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 636.280s 8038.289us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 280.060s 6822.760us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 280.060s 6822.760us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 227.110s 4171.277us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 351.460s 7243.175us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 216.540s 4711.141us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 215.210s 4461.894us 1 1 100.00
chip_tap_straps_testunlock0 220.420s 5143.176us 1 1 100.00
chip_tap_straps_rma 282.930s 5623.936us 1 1 100.00
chip_tap_straps_prod 110.230s 3130.557us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 418.020s 6819.018us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 418.020s 6819.018us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 608.080s 7770.997us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1421.080s 15044.409us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 346.030s 5121.058us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 569.160s 6637.167us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4160.660s 20815.213us 1 1 100.00
chip_sw_aes_enc_jitter_en 181.730s 3324.266us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 693.370s 6509.612us 1 1 100.00
chip_sw_hmac_enc_jitter_en 194.530s 3102.121us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1322.590s 11034.236us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 235.970s 3527.750us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 452.090s 6469.852us 1 1 100.00
chip_sw_clkmgr_jitter 137.030s 3346.748us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 212.380s 4009.134us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 482.470s 8492.530us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 249.880s 6114.441us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 199.790s 3974.451us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 249.880s 6114.441us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 182.280s 3974.892us 1 1 100.00
chip_sw_aes_smoketest 165.910s 3194.909us 1 1 100.00
chip_sw_aon_timer_smoketest 169.820s 3359.007us 1 1 100.00
chip_sw_clkmgr_smoketest 146.130s 2505.170us 1 1 100.00
chip_sw_csrng_smoketest 162.440s 3596.470us 1 1 100.00
chip_sw_entropy_src_smoketest 839.530s 7189.292us 1 1 100.00
chip_sw_gpio_smoketest 206.180s 3052.390us 1 1 100.00
chip_sw_hmac_smoketest 200.780s 4348.994us 1 1 100.00
chip_sw_kmac_smoketest 172.440s 2875.567us 1 1 100.00
chip_sw_otbn_smoketest 1424.600s 10807.722us 1 1 100.00
chip_sw_pwrmgr_smoketest 386.290s 8137.718us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 321.260s 6316.982us 1 1 100.00
chip_sw_rv_plic_smoketest 185.430s 3753.846us 1 1 100.00
chip_sw_rv_timer_smoketest 158.790s 3773.678us 1 1 100.00
chip_sw_rstmgr_smoketest 157.290s 3404.174us 1 1 100.00
chip_sw_sram_ctrl_smoketest 155.700s 3600.770us 1 1 100.00
chip_sw_uart_smoketest 169.240s 3962.160us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 210.780s 3764.181us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 287.900s 4774.452us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8134.910s 60686.854us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3454.180s 16899.610us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 11.438s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1081.830s 15208.485us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 940.230s 15307.524us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7320.690s 53053.141us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7796.820s 57204.382us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 67.020s 2249.929us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 67.020s 2249.929us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3139.510s 27585.234us 1 1 100.00
chip_same_csr_outstanding 2183.630s 27653.519us 1 1 100.00
chip_csr_hw_reset 303.140s 8217.986us 1 1 100.00
chip_csr_rw 418.450s 5578.651us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3139.510s 27585.234us 1 1 100.00
chip_same_csr_outstanding 2183.630s 27653.519us 1 1 100.00
chip_csr_hw_reset 303.140s 8217.986us 1 1 100.00
chip_csr_rw 418.450s 5578.651us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 35.790s 1300.337us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.120s 43.272us 1 1 100.00
xbar_smoke_large_delays 54.320s 9120.543us 1 1 100.00
xbar_smoke_slow_rsp 50.090s 5013.570us 1 1 100.00
xbar_random_zero_delays 25.280s 404.646us 1 1 100.00
xbar_random_large_delays 161.230s 27808.513us 1 1 100.00
xbar_random_slow_rsp 78.320s 9002.377us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 26.130s 784.578us 1 1 100.00
xbar_error_and_unmapped_addr 33.540s 1254.247us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 55.940s 2004.314us 1 1 100.00
xbar_error_and_unmapped_addr 33.540s 1254.247us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 41.210s 739.424us 1 1 100.00
xbar_access_same_device_slow_rsp 581.300s 69092.662us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 24.670s 1243.432us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 83.920s 3776.911us 1 1 100.00
xbar_stress_all_with_error 28.060s 1201.816us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 532.390s 14753.302us 1 1 100.00
xbar_stress_all_with_reset_error 412.550s 5972.393us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3454.180s 16899.610us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 612.950s 13454.584us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 525.430s 6975.644us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 24.033s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 20.417s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 15.204s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 14.076s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 16.683s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 113.996s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 78.561s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 31.062s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 64.893s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 10.469s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 161.958s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 40.556s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 51.921s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 28.740s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 17.047s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 19.980s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 20.420s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 20.300s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 21.300s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 19.980s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 26.120s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 19.550s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 21.080s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 20.400s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 20.970s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 20.390s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 19.270s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 20.340s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 19.810s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 24.390s 10.340us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 46.898s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 56.613s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 91.980s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 64.437s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 44.963s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 3389.970s 19955.097us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 6194.850s 31209.197us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6176.200s 28394.908us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3436.040s 20780.727us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3216.330s 35641.279us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3216.330s 35641.279us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 153.150s 3307.691us 1 1 100.00
chip_sw_aes_enc_jitter_en 181.730s 3324.266us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 213.600s 3712.883us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 157.130s 3581.062us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1052.560s 9485.920us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 196.990s 3281.799us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 370.640s 6445.084us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 449.490s 7176.511us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 523.320s 5419.940us 1 1 100.00
chip_plic_all_irqs_10 288.440s 3857.876us 1 1 100.00
chip_plic_all_irqs_20 385.890s 5291.803us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 194.650s 3595.475us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1316.260s 15416.540us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 298.540s 6147.706us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 182.220s 3785.904us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.141s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1116.820s 8844.716us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 883.750s 8382.478us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 871.910s 8573.954us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9335.750s 257129.012us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 293.670s 4775.396us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 386.290s 8137.718us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 293.670s 4775.396us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 488.560s 9205.100us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 488.560s 9205.100us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 334.270s 8097.497us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 447.920s 7205.529us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 611.630s 6208.017us 1 1 100.00
chip_sw_aes_idle 157.130s 3581.062us 1 1 100.00
chip_sw_hmac_enc_idle 199.550s 4091.011us 1 1 100.00
chip_sw_kmac_idle 166.530s 3289.641us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 334.940s 5954.560us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 332.490s 4574.711us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 290.960s 6466.398us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 283.190s 5202.179us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 929.290s 11657.268us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 407.830s 4845.401us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 430.770s 5485.916us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 368.950s 3986.895us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 371.460s 5166.971us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 383.460s 3993.764us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 407.670s 5316.559us 1 1 100.00
chip_sw_ast_clk_outputs 608.080s 7770.997us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 920.260s 19251.768us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 368.950s 3986.895us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 371.460s 5166.971us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 346.030s 5121.058us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 569.160s 6637.167us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4160.660s 20815.213us 1 1 100.00
chip_sw_aes_enc_jitter_en 181.730s 3324.266us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 693.370s 6509.612us 1 1 100.00
chip_sw_hmac_enc_jitter_en 194.530s 3102.121us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1322.590s 11034.236us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 235.970s 3527.750us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 452.090s 6469.852us 1 1 100.00
chip_sw_clkmgr_jitter 137.030s 3346.748us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 149.930s 3163.587us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 393.830s 5409.971us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 596.070s 7532.100us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4432.540s 25579.898us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 179.240s 3295.717us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 156.210s 3477.624us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 778.730s 9673.251us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 172.640s 4587.747us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 474.100s 6462.671us 1 1 100.00
chip_sw_flash_init_reduced_freq 1244.720s 21969.143us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3463.130s 24585.481us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 608.080s 7770.997us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 404.330s 5341.784us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 262.860s 3913.013us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 449.490s 7176.511us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1116.820s 8844.716us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2202.350s 24898.553us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 146.470s 3139.358us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 628.880s 10588.389us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 206.720s 3233.586us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2425.510s 14110.313us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 130.400s 3267.990us 1 1 100.00
chip_sw_edn_entropy_reqs 639.930s 6469.944us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 130.400s 3267.990us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2202.350s 24898.553us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 162.340s 3514.170us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1406.200s 32103.295us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 576.220s 5166.466us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 569.160s 6637.167us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 414.270s 4096.636us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 346.030s 5121.058us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3648.070s 43173.677us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1406.200s 32103.295us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 242.250s 3628.013us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1020.300s 8820.573us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 173.060s 3725.268us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3648.070s 43173.677us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 173.060s 3725.268us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 173.060s 3725.268us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 173.060s 3725.268us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 173.060s 3725.268us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 449.490s 7176.511us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 422.620s 16188.471us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 544.160s 5406.540us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 482.080s 7102.267us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 482.080s 7102.267us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 223.890s 3292.449us 1 1 100.00
chip_sw_hmac_enc_jitter_en 194.530s 3102.121us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 199.550s 4091.011us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1526.550s 11225.899us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1680.040s 12018.563us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 439.600s 5856.212us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 399.340s 5832.670us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 414.030s 5516.600us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 321.670s 4744.743us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1020.300s 8820.573us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1322.590s 11034.236us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1758.760s 12172.160us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1052.560s 9485.920us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4511.550s 20026.754us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 145.330s 3189.955us 1 1 100.00
chip_sw_kmac_mode_kmac 196.470s 3478.027us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 235.970s 3527.750us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1020.300s 8820.573us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 373.670s 8700.904us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 208.450s 3345.141us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 996.700s 7485.786us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 166.530s 3289.641us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 370.640s 6445.084us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 215.210s 4461.894us 1 1 100.00
chip_tap_straps_rma 282.930s 5623.936us 1 1 100.00
chip_tap_straps_prod 110.230s 3130.557us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 162.240s 2761.590us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 373.670s 8700.904us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 373.670s 8700.904us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 373.670s 8700.904us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1826.970s 13845.178us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 173.060s 3725.268us 0 1 0.00
chip_sw_flash_rma_unlocked 3648.070s 43173.677us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 242.430s 3799.268us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 502.240s 7183.437us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 550.500s 8624.650us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 548.780s 7284.779us 0 1 0.00
chip_sw_lc_ctrl_transition 373.670s 8700.904us 1 1 100.00
chip_sw_keymgr_key_derivation 1020.300s 8820.573us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 302.280s 11198.699us 1 1 100.00
chip_sw_sram_ctrl_execution_main 542.730s 10810.817us 1 1 100.00
chip_prim_tl_access 422.620s 16188.471us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 920.260s 19251.768us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 407.830s 4845.401us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 430.770s 5485.916us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 368.950s 3986.895us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 371.460s 5166.971us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 383.460s 3993.764us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 407.670s 5316.559us 1 1 100.00
chip_tap_straps_dev 215.210s 4461.894us 1 1 100.00
chip_tap_straps_rma 282.930s 5623.936us 1 1 100.00
chip_tap_straps_prod 110.230s 3130.557us 1 1 100.00
chip_rv_dm_lc_disabled 170.820s 5705.284us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 187.170s 3781.156us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 133.520s 4617.945us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 131.350s 4529.040us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 125.060s 3906.363us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1600.680s 33587.929us 1 1 100.00
chip_rv_dm_lc_disabled 170.820s 5705.284us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 737.310s 15925.031us 0 1 0.00
chip_sw_lc_walkthrough_prod 659.020s 10798.426us 0 1 0.00
chip_sw_lc_walkthrough_prodend 821.760s 14269.296us 1 1 100.00
chip_sw_lc_walkthrough_rma 472.560s 9847.566us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1600.680s 33587.929us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 1 3 33.33
chip_sw_lc_ctrl_volatile_raw_unlock 1018.510s 26350.163us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 84.030s 3446.737us 1 1 100.00
rom_volatile_raw_unlock 88.491s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3910.920s 17348.919us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4160.660s 20815.213us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 611.630s 6208.017us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 611.630s 6208.017us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 611.630s 6208.017us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 315.200s 4473.319us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 373.670s 8700.904us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1406.200s 32103.295us 1 1 100.00
chip_sw_otbn_mem_scramble 315.200s 4473.319us 1 1 100.00
chip_sw_keymgr_key_derivation 1020.300s 8820.573us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 445.610s 5320.293us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 224.040s 4093.064us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1406.200s 32103.295us 1 1 100.00
chip_sw_otbn_mem_scramble 315.200s 4473.319us 1 1 100.00
chip_sw_keymgr_key_derivation 1020.300s 8820.573us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 445.610s 5320.293us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 224.040s 4093.064us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 373.670s 8700.904us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 369.590s 6575.900us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 162.240s 2761.590us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 242.430s 3799.268us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 502.240s 7183.437us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 550.500s 8624.650us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 548.780s 7284.779us 0 1 0.00
chip_sw_lc_ctrl_transition 373.670s 8700.904us 1 1 100.00
chip_prim_tl_access 422.620s 16188.471us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 422.620s 16188.471us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 897.420s 9463.218us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 75.610s 2158.263us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1013.250s 29429.195us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 216.560s 8179.196us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 306.890s 8622.036us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 481.390s 7300.982us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1117.830s 26304.477us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 263.070s 6572.864us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 488.560s 9205.100us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1076.980s 15514.821us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 351.750s 7089.121us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 75.610s 2158.263us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 383.030s 6745.301us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 732.770s 14857.506us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 346.070s 7829.087us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 133.500s 2972.437us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 273.620s 7363.749us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 528.200s 7230.809us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1133.890s 14688.805us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1687.840s 33944.188us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 216.150s 3474.118us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 449.490s 7176.511us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 302.280s 11198.699us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 302.280s 11198.699us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1133.890s 14688.805us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 273.620s 7363.749us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 351.750s 7089.121us 1 1 100.00
chip_sw_pwrmgr_smoketest 386.290s 8137.718us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 363.700s 6537.487us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 497.250s 8080.124us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 407.790s 5811.083us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1316.260s 15416.540us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 212.310s 3349.965us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 449.490s 7176.511us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 883.750s 8382.478us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 486.770s 5575.375us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 507.730s 5210.289us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 214.050s 3929.933us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 224.040s 4093.064us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 497.250s 8080.124us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 497.250s 8080.124us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 155.980s 2953.371us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1100.030s 17048.485us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 845.810s 14728.942us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 363.700s 6537.487us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 209.820s 3093.010us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 177.820s 2971.774us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 282.930s 5623.936us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 170.820s 5705.284us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 523.320s 5419.940us 1 1 100.00
chip_plic_all_irqs_10 288.440s 3857.876us 1 1 100.00
chip_plic_all_irqs_20 385.890s 5291.803us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 181.750s 3961.790us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 155.070s 4016.669us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3454.180s 16899.610us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 231.760s 4566.074us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 241.970s 3740.132us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 209.600s 4038.687us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 188.640s 3859.872us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 445.610s 5320.293us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 452.090s 6469.852us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 449.350s 9899.951us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 627.840s 10540.256us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 542.730s 10810.817us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 449.490s 7176.511us 1 1 100.00
chip_sw_data_integrity_escalation 418.020s 6819.018us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 528.200s 7230.809us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1063.730s 24576.007us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 186.520s 3727.791us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 233.990s 3442.491us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 319.460s 4317.727us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 1063.730s 24576.007us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 1063.730s 24576.007us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2467.710s 21023.134us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2467.710s 21023.134us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 327.120s 6363.925us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3216.330s 35641.279us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 190.420s 4150.681us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 168.710s 2926.472us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 366.810s 4845.275us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 347.930s 4801.775us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 996.330s 8088.134us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5192.290s 32233.286us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2019.730s 12855.240us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 197.530s 4258.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 225.570s 3402.092us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 94.950s 3192.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9981.700s 68251.839us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1169.120s 6616.051us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 497.520s 7807.645us 0 1 0.00
rom_e2e_jtag_debug_dev 205.100s 4173.999us 0 1 0.00
rom_e2e_jtag_debug_rma 196.580s 5869.350us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 90.660s 2227.300us 0 1 0.00
rom_e2e_jtag_inject_dev 96.120s 2699.714us 0 1 0.00
rom_e2e_jtag_inject_rma 102.710s 3262.373us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 19.159s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 266.960s 3744.761us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 318.050s 3693.986us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 850.460s 6018.114us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1685.020s 11400.768us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 263.480s 2497.589us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 593.100s 5317.175us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 86.800s 2206.089us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 218.890s 3661.390us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 329.400s 6637.559us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 368.120s 6422.485us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1133.890s 14688.805us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 497.520s 7807.645us 0 1 0.00
rom_e2e_jtag_debug_dev 205.100s 4173.999us 0 1 0.00
rom_e2e_jtag_debug_rma 196.580s 5869.350us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 391.050s 6451.137us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 449.490s 7176.511us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5687.420s 38597.962us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5687.420s 38597.962us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 198.670s 4357.962us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 353.060s 4463.825us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2946.070s 20081.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 236.200s 3577.475us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 21.380s 10.260us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 6.470s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 177.740s 2608.737us 1 1 100.00
chip_sw_otp_ctrl_descrambling 203.650s 3547.784us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 265.560s 4232.723us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.647s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 204.270s 3449.504us 1 1 100.00
ate_bootstrap_flash_erase 674.720s 10010.300us 0 1 0.00
ate_bootstrap_one_frame 6236.300s 43605.345us 1 1 100.00
ate_bootstrap_disjoint 9189.470s 80152.411us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 93633269140093670170521227579393149881451621484505928128412949309676321237963 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 64121062889897942888062681859018567976271664882254840553096167455553330178098 None
Another command (pid=376351) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=379686) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=441700) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 79204227629557093282830707405045755131359370773727252776184371655314029700364 None
Another command (pid=611144) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=620751) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=553313) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 82098589471856548405679694411538179105125810758502006969729189085718504721152 None
Another command (pid=487535) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=606909) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=611144) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 94253604638300288328535625793473416235769638615985922175610012901168720002675 None
Another command (pid=576452) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=487535) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=606909) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 106883416354712142354250350157380091321814734157032381493044328252329615237568 None
Another command (pid=553313) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=594565) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=635381) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 90366802230918317795940700827145414271591343629900461548101206013636552827897 None
Another command (pid=430234) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=444563) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=471118) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 75066858458814895308809950087147699622204278246105664163413140342582057393295 None
Another command (pid=714944) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=720522) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=731817) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 114074097805978447362464114331799540998344179549297907901774808469165732790466 None
Another command (pid=553313) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=594565) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=635381) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 28242001363148524495047367861378848647542133735480554913676430822569083646967 None
Another command (pid=717386) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=725633) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=724641) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 66184897210572092751967631755613442794637683188021829477698713627711845936082 None
Another command (pid=595195) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=554487) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=581811) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 56936004440448676580239062104207024123997531144496536678309134496607453080981 None
Another command (pid=487535) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=606909) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=593378) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 111355219865902532117805014041307289894157512261168484453390112524329518770487 None
Another command (pid=593946) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=579220) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=595195) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 97632320860083562903351110285474679221169596182412853297031176129620982402252 None
---- STDERR ----
Another command (pid=651768) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 60146789740659646448229124566279812488592685522412154624240522723984638597911 None
Another command (pid=579220) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=595195) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=394597) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 13828354568906843361063644436976879696709593521826991351665273414183076326214 None
Another command (pid=454948) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=555666) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=580145) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 112523294633000947013630353183519403005533303657216557616104314094997970364388 None
---- STDERR ----
Another command (pid=376351) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=379686) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 114185015193494702879521097932827203075358010355053399694905927500231444398348 None
---- STDERR ----
Another command (pid=444563) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=471118) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 9706330961658873580324088030182644282663407417796010890007696018927699993481 None
Another command (pid=581811) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=604694) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=577620) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 76962473340530447618603977232425888915884816375644688645556278325170319730887 None
Another command (pid=569285) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=454786) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=566467) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 45778152554162468803411359843362285083219142140442383573732192777162601439829 None
Another command (pid=471118) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=400185) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=455696) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 12315359130548502726019655818159089000390398237954611368912425293074862028151 None
Another command (pid=562359) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=565399) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=569285) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 22378621983970742500314484510289994939872959602369904006353615630012263192311 None
Another command (pid=376351) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=379686) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=387174) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 81695065905800761984918992977637962420313926971503357975389892102784024462964 None
---- STDERR ----
Another command (pid=376351) is running. Waiting for it to complete on the server (server_pid=273572)...
Another command (pid=379686) is running. Waiting for it to complete on the server (server_pid=273572)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 17856905526887948561342639093873557756653669400765699850528253320979696169982 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 44171359527879994375387564139528304631681124679075245599308421670005016078952 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 29587808376748708466632849601115450606841444702611396396549609285787923341122 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 22291438897929609590519358651905563842751772666198560825176692607138738997592 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 38389120344112719569444122358821820743524351057417646933572511028970739846149 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 73431897129594188514228876082849855739446295039522764756350965263323987577894 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 78072735016045345394034731321331515397178627225880126907388438069690381638791 365
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 97002169383810686799382336516357205651916006110879132499065062782857562665593 368
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 72506784416367211955095236603421777305849713953106006974323407483472327445316 363
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 42490861026753191081487419315797958810073078705567045836297952448360901657081 328
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 68425382434675866451349163689572033646241393026008579920308709723265899126330 327
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 97550325336078870832126230946400085995587813890585837852228328131831444982312 328
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 76839245634935294588512203527478649540239672433321084130418998582585877419059 315
UVM_ERROR @ 7363.749000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7363.749000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 64181951673114724755423590470616925151228212683908011334738106635546253469776 314
UVM_ERROR @ 6572.864000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6572.864000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 40452535484541531499533907625687227454733579339928552655494640210689072767680 325
UVM_ERROR @ 8622.036000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8622.036000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 45256914125139259790346141475300049827059103211289078704857071931129995901108 334
UVM_ERROR @ 24576.007000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 24576.007000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 108512452807782998556863779371110739942355174969424532984452156040477107544008 319
UVM_ERROR @ 9205.100000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9205.100000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 4294577771075667320289103161054763947213403125364347927956513597167576916798 369
UVM_INFO @ 15925.030700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 51965519695194026284448362225650093853645557439545918535358061116599640178374 369
UVM_INFO @ 10798.426152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 33204294312574147627227846623108831647210902247518095439836945694717516114980 341
UVM_INFO @ 9847.566091 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 67109466891603049892425477235487689019461036738276527607742892125107967277344 328
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 53395456424653718337100496051730845490790791333454225288082200733812830299380 327
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 92483330543856545723108153130540686006432697254085209678562270210401916343674 328
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 9784517316980654368909313640155677989451120723238495390265523294972098381155 316
UVM_ERROR @ 3661.390258 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3661.390258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 82066245685138132606053763572128227129027253599998892742820864767895884088847 312
UVM_ERROR @ 3139.358376 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3139.358376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 62736960013000392143859973358253436791101613705061884050912690191790216780784 313
UVM_ERROR @ 2972.436949 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2972.436949 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 115450219389219082922516781945225632594254152693395865686178395604341419378725 355
UVM_ERROR @ 14857.506309 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 14857.506309 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 114190595351725096436455453029318177704554245186875349643161422244425331913130 363
UVM_INFO @ 12018.563041 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 115166287600662607446586966468113943825166555708797292844473948661319539475398 336
UVM_INFO @ 20026.753587 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 106418824264711705876603976075662931553465446936213116576267313747613972388224 362
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 78804771923850389227692120809421808320503709896659662543105501546899732961916 325
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 66048917733143007685148241847317333341115311150428529177031460997852349104916 368
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 78213527359479145304029596045412791928692053067545756404929431695601008128184 327
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 56497225176096084511155408333364349979163515045825415866109904786592023325692 301
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 35006922619185594842120666773938741910508529895357558239193695890558143637794 327
UVM_INFO @ 3740.131888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 85589887895979196612795646674579640649320919109212498707077106831683692184228 309
UVM_INFO @ 3725.267910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 89968541373981790075385543013106142516270117056366885185502332151624467991554 342
UVM_INFO @ 7284.778836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 71184830407764585771315105965393042902783286597819116275276974023723740992877 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcTokenError! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock 28291447782404778335865621427330777510643242235222856451686114336913151474726 308
UVM_INFO @ 26350.163470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 69024125287387175024332665702150013501678907987867730979379190600548236774148 303
UVM_ERROR @ 2158.262985 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2158.262985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 14613609850397948554134694485292810150170285058817788201443715893286853129303 332
UVM_INFO @ 35641.278547 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:402)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 25789016444690127368588919767651245252310774983621055771290534022230968061060 307
UVM_INFO @ 3281.799437 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 22210450354723503262057011267926433372740330096676784231333972879449219267607 308
UVM_INFO @ 3785.904264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 114325919316403017652739246362467856990794848481918926609862343623173803415374 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
chip_tl_errors 45555431030177904334913267279847415073442425664420599397910366578835181926391 217
TL item was: req: (cip_tl_seq_item@33777) { a_addr: 'h10478 a_data: 'he0f7b286 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h195d9 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2249.928572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 27549259782495863676718755519011866669774291906974494670203612706219516207807 343
UVM_INFO @ 3744.761045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * straight after write. 1 test run
chip_sw_rv_dm_access_after_wakeup 13766769066257461686625837418680206856536191292482694798308604782931544356493 309
UVM_INFO @ 2971.773684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 34802678394753130943470898707860061865041708868288852474988895539106141972698 225
UVM_INFO @ 5705.283860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 63419337940506156962983972561335201282105831207497663409562049264972545334477 318
UVM_INFO @ 15208.485342 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 53366045838978092342720571524773003298183354064053469957088766330648813220462 329
UVM_INFO @ 15307.524055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 74073950621083691898797120246545527090367629909751708959995957722325922447253 327
UVM_INFO @ 15044.408860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 62916602447685415139620733080438194578135677074004953715288803050864416435778 272
UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_exception_c 8061566092786785510512104444961285371290091863412346254043505921096431884588 319
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 6975.643665 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_output 9899078576389291237926309440060439723256462216716512650192248388805110190576 312
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 13454.584137 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 41556463596971698837141845744086252997350919343894547277777684715836966178601 325
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 48942379566335796517744968748034842595291146029405958019164503779771991698633 328
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*]) 1 test run
rom_e2e_jtag_debug_dev 54141267284496364963953418904606188601591765875218074886934508800219804707203 317
UVM_INFO @ 4173.998569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_meas 108323794824180902847898143888558726194449486182644008021068619655070388743716 319
UVM_INFO @ 19955.097352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 29907354770946064730357397933274215801805836324443273741147144666241132153756 327
UVM_ERROR @ 4774.451976 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4774.451976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---