Simulation Results: clkmgr

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.55 %
  • code
  • 97.72 %
  • assert
  • 94.07 %
  • func
  • 82.85 %
  • line
  • 98.88 %
  • branch
  • 98.64 %
  • cond
  • 91.91 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.880s 79.461us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.680s 16.521us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.890s 22.726us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.350s 321.411us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.920s 24.385us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.180s 69.329us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.890s 22.726us 1 1 100.00
clkmgr_csr_aliasing 0.920s 24.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.700s 22.744us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.020s 54.860us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.050s 44.076us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.810s 20.261us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.880s 79.461us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 11.630s 2477.651us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.900s 1108.578us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 11.630s 2477.651us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 0.830s 35.579us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.280s 254.886us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.790s 1062.964us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.790s 1062.964us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.680s 16.521us 1 1 100.00
clkmgr_csr_rw 0.890s 22.726us 1 1 100.00
clkmgr_csr_aliasing 0.920s 24.385us 1 1 100.00
clkmgr_same_csr_outstanding 1.180s 39.263us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.680s 16.521us 1 1 100.00
clkmgr_csr_rw 0.890s 22.726us 1 1 100.00
clkmgr_csr_aliasing 0.920s 24.385us 1 1 100.00
clkmgr_same_csr_outstanding 1.180s 39.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 22.770s 10192.644us 0 1 0.00
clkmgr_tl_intg_err 1.540s 123.470us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.180s 91.231us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.180s 91.231us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.180s 91.231us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.180s 91.231us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 5.220s 2106.429us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.540s 123.470us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 11.630s 2477.651us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.900s 1108.578us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.180s 91.231us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.720s 22.883us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.740s 20.067us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.740s 23.562us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.740s 17.378us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.000s 53.151us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.890s 22.726us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 22.770s 10192.644us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 22.726us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.890s 22.726us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 22.770s 10192.644us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.190s 219.057us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 18.950s 4484.975us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_enable (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 114055281726194789112464866751521181749770796242540864600262496456398577915951 75
UVM_INFO @ 2106428713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 28656142569871029561940867685470668798104682261075683139373653035509431908406 129
UVM_INFO @ 10192644194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---