Simulation Results: edn/edn0

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.27 %
  • code
  • 80.43 %
  • assert
  • 95.01 %
  • func
  • 80.36 %
  • line
  • 97.17 %
  • branch
  • 90.24 %
  • cond
  • 85.14 %
  • toggle
  • 82.28 %
  • FSM
  • 47.31 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.110s 44.967us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.960s 36.999us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.230s 49.308us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.880s 170.546us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.020s 16.009us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.990s 101.226us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.230s 49.308us 1 1 100.00
edn_csr_aliasing 1.020s 16.009us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.040s 140.980us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.040s 140.980us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.040s 140.980us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.060s 24.413us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.050s 36.312us 1 1 100.00
errs 1 1 100.00
edn_err 0.880s 27.600us 1 1 100.00
disable 2 2 100.00
edn_disable 0.830s 12.210us 1 1 100.00
edn_disable_auto_req_mode 0.970s 92.713us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.090s 129.122us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.890s 65.231us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 27.566us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.850s 64.903us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.850s 64.903us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.960s 36.999us 1 1 100.00
edn_csr_rw 1.230s 49.308us 1 1 100.00
edn_csr_aliasing 1.020s 16.009us 1 1 100.00
edn_same_csr_outstanding 0.970s 33.016us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.960s 36.999us 1 1 100.00
edn_csr_rw 1.230s 49.308us 1 1 100.00
edn_csr_aliasing 1.020s 16.009us 1 1 100.00
edn_same_csr_outstanding 0.970s 33.016us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.000s 312.872us 1 1 100.00
edn_tl_intg_err 2.180s 104.106us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.910s 17.151us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.050s 36.312us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 312.872us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 312.872us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 312.872us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 312.872us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.050s 36.312us 1 1 100.00
edn_sec_cm 4.000s 312.872us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.050s 36.312us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.180s 104.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 65.730s 3871.598us 1 1 100.00