Simulation Results: edn/edn1

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.89 %
  • code
  • 81.95 %
  • assert
  • 97.14 %
  • func
  • 78.57 %
  • line
  • 97.80 %
  • branch
  • 92.86 %
  • cond
  • 89.38 %
  • toggle
  • 86.52 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 30.492us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.750s 42.042us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.890s 15.947us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.910s 2284.871us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.240s 28.288us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.180s 81.796us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.890s 15.947us 1 1 100.00
edn_csr_aliasing 1.240s 28.288us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.860s 64.244us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.860s 64.244us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.860s 64.244us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 19.830us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.200s 46.298us 1 1 100.00
errs 1 1 100.00
edn_err 0.890s 65.368us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 20.874us 1 1 100.00
edn_disable_auto_req_mode 0.920s 118.232us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.280s 123.019us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.870s 18.444us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.780s 40.566us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.400s 180.094us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.400s 180.094us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.750s 42.042us 1 1 100.00
edn_csr_rw 0.890s 15.947us 1 1 100.00
edn_csr_aliasing 1.240s 28.288us 1 1 100.00
edn_same_csr_outstanding 0.960s 34.842us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.750s 42.042us 1 1 100.00
edn_csr_rw 0.890s 15.947us 1 1 100.00
edn_csr_aliasing 1.240s 28.288us 1 1 100.00
edn_same_csr_outstanding 0.960s 34.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.480s 202.275us 1 1 100.00
edn_tl_intg_err 1.950s 774.956us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.900s 19.539us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.200s 46.298us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.480s 202.275us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.480s 202.275us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.480s 202.275us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.480s 202.275us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.200s 46.298us 1 1 100.00
edn_sec_cm 2.480s 202.275us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.200s 46.298us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.950s 774.956us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 27.110s 6760.702us 1 1 100.00