Simulation Results: flash_ctrl

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.43 %
  • code
  • 93.36 %
  • assert
  • 96.94 %
  • func
  • 95.98 %
  • line
  • 95.93 %
  • branch
  • 97.06 %
  • cond
  • 93.61 %
  • toggle
  • 95.84 %
  • FSM
  • 84.35 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 88.850s 92.690us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.780s 16.817us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 15.170s 274.601us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.530s 41.678us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 61.930s 3534.691us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 20.550s 607.548us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.220s 90.210us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.530s 41.678us 1 1 100.00
flash_ctrl_csr_aliasing 20.550s 607.548us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.540s 38.360us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 7.190s 29.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 13.850s 29.127us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 35.750s 114.120us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1292.550s 170055.186us 1 1 100.00
flash_ctrl_hw_rma_reset 529.060s 90164.023us 1 1 100.00
flash_ctrl_lcmgr_intg 6.120s 23.606us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 973.670s 546070.341us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 171.410s 3707.086us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.430s 21.465us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1763.590s 111887.762us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 87.410s 5652.120us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.330s 33.587us 1 1 100.00
flash_ctrl_rw_evict_all_en 16.680s 124.634us 1 1 100.00
flash_ctrl_re_evict 17.720s 150.480us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 186.390s 2786.700us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 186.390s 2786.700us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 100.920s 2394.396us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 14.480s 191.643us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 200.520s 78.045us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 434.400s 4422.119us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 325.910s 1335.571us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 810.170s 601.824us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.120s 30.904us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 128.320s 3321.311us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 13.210s 37.711us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.100s 28.961us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 408.270s 566.192us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 91.640s 17410.237us 1 1 100.00
flash_ctrl_otp_reset 65.040s 586.161us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1292.550s 170055.186us 1 1 100.00
interrupts 3 4 75.00
flash_ctrl_intr_rd 88.660s 5871.239us 1 1 100.00
flash_ctrl_intr_wr 3603.776s 0.000us 0 1 0.00
flash_ctrl_intr_rd_slow_flash 183.480s 62734.504us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 153.700s 47173.394us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 48.250s 3990.358us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.250s 2864.588us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 16.800s 108.050us 1 1 100.00
flash_ctrl_ro_derr 118.970s 4444.417us 1 1 100.00
flash_ctrl_rw_derr 165.390s 8912.307us 1 1 100.00
flash_ctrl_derr_detect 90.140s 528.231us 1 1 100.00
flash_ctrl_integrity 385.020s 4991.145us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 13.830s 31.382us 1 1 100.00
flash_ctrl_ro_serr 88.890s 972.726us 1 1 100.00
flash_ctrl_rw_serr 137.090s 1667.216us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 58.260s 5788.744us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 50.620s 904.026us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 100.370s 11065.161us 1 1 100.00
flash_ctrl_write_word_sweep 7.550s 152.737us 1 1 100.00
flash_ctrl_read_word_sweep 7.180s 54.390us 1 1 100.00
flash_ctrl_ro 90.350s 14573.965us 1 1 100.00
flash_ctrl_rw 379.240s 4390.818us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 20.210s 1023.855us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 565.570s 41639.536us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 24.560s 10070.725us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.150s 668.587us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.260s 62.057us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.560s 80.813us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.560s 80.813us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.170s 274.601us 1 1 100.00
flash_ctrl_csr_rw 9.530s 41.678us 1 1 100.00
flash_ctrl_csr_aliasing 20.550s 607.548us 1 1 100.00
flash_ctrl_same_csr_outstanding 6.940s 72.604us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.170s 274.601us 1 1 100.00
flash_ctrl_csr_rw 9.530s 41.678us 1 1 100.00
flash_ctrl_csr_aliasing 20.550s 607.548us 1 1 100.00
flash_ctrl_same_csr_outstanding 6.940s 72.604us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 8.610s 73.934us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 8.610s 73.934us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 8.610s 73.934us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 8.610s 73.934us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 75.950s 1020.691us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1742.290s 7698.883us 1 1 100.00
flash_ctrl_tl_intg_err 209.950s 772.662us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 209.950s 772.662us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 209.950s 772.662us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.110s 73.184us 1 1 100.00
flash_ctrl_wr_intg 8.880s 50.500us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 88.850s 92.690us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 65.040s 586.161us 1 1 100.00
flash_ctrl_disable 13.210s 37.711us 1 1 100.00
flash_ctrl_sec_info_access 42.680s 1933.841us 1 1 100.00
flash_ctrl_connect 6.100s 28.961us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.990s 161.181us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.530s 41.678us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 8.610s 73.934us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.530s 41.678us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 8.610s 73.934us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.530s 41.678us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 8.610s 73.934us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 13.210s 37.711us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.110s 73.184us 1 1 100.00
flash_ctrl_access_after_disable 7.850s 261.760us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.580s 28.469us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 13.210s 37.711us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 14.480s 191.643us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 379.240s 4390.818us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 137.090s 1667.216us 1 1 100.00
flash_ctrl_rw_derr 165.390s 8912.307us 1 1 100.00
flash_ctrl_integrity 385.020s 4991.145us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1292.550s 170055.186us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1742.290s 7698.883us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1742.290s 7698.883us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1742.290s 7698.883us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1742.290s 7698.883us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.180s 914.096us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 8.970s 70.696us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 9.120s 441.151us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1742.290s 7698.883us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1742.290s 7698.883us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1742.290s 7698.883us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 28.100s 375.290us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 205.070s 974.694us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
flash_ctrl_intr_wr 5631313033314815617897625071196311534882709598846751462476169115235323151348 None