Simulation Results: hmac

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.54 %
  • code
  • 97.71 %
  • assert
  • 97.60 %
  • func
  • 43.32 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.73 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.620s 151.008us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.190s 40.937us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.830s 22.841us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.600s 4527.945us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.540s 1392.960us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.740s 42.927us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.830s 22.841us 1 1 100.00
hmac_csr_aliasing 4.540s 1392.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 68.400s 8483.092us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 23.670s 772.837us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 205.500s 38117.394us 1 1 100.00
hmac_test_sha384_vectors 457.910s 407717.324us 1 1 100.00
hmac_test_sha512_vectors 20.660s 2460.076us 1 1 100.00
hmac_test_hmac256_vectors 11.790s 3105.501us 1 1 100.00
hmac_test_hmac384_vectors 7.200s 563.734us 1 1 100.00
hmac_test_hmac512_vectors 11.470s 1735.446us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 4.210s 139.728us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 0.820s 85.545us 1 1 100.00
error 1 1 100.00
hmac_error 15.390s 544.333us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 102.420s 15282.081us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.620s 151.008us 1 1 100.00
hmac_long_msg 68.400s 8483.092us 1 1 100.00
hmac_back_pressure 23.670s 772.837us 1 1 100.00
hmac_datapath_stress 0.820s 85.545us 1 1 100.00
hmac_burst_wr 4.210s 139.728us 1 1 100.00
hmac_stress_all 1481.610s 590165.329us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.620s 151.008us 1 1 100.00
hmac_long_msg 68.400s 8483.092us 1 1 100.00
hmac_back_pressure 23.670s 772.837us 1 1 100.00
hmac_datapath_stress 0.820s 85.545us 1 1 100.00
hmac_wipe_secret 102.420s 15282.081us 1 1 100.00
hmac_test_sha256_vectors 205.500s 38117.394us 1 1 100.00
hmac_test_sha384_vectors 457.910s 407717.324us 1 1 100.00
hmac_test_sha512_vectors 20.660s 2460.076us 1 1 100.00
hmac_test_hmac256_vectors 11.790s 3105.501us 1 1 100.00
hmac_test_hmac384_vectors 7.200s 563.734us 1 1 100.00
hmac_test_hmac512_vectors 11.470s 1735.446us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.620s 151.008us 1 1 100.00
hmac_long_msg 68.400s 8483.092us 1 1 100.00
hmac_back_pressure 23.670s 772.837us 1 1 100.00
hmac_datapath_stress 0.820s 85.545us 1 1 100.00
hmac_burst_wr 4.210s 139.728us 1 1 100.00
hmac_error 15.390s 544.333us 1 1 100.00
hmac_wipe_secret 102.420s 15282.081us 1 1 100.00
hmac_test_sha256_vectors 205.500s 38117.394us 1 1 100.00
hmac_test_sha384_vectors 457.910s 407717.324us 1 1 100.00
hmac_test_sha512_vectors 20.660s 2460.076us 1 1 100.00
hmac_test_hmac256_vectors 11.790s 3105.501us 1 1 100.00
hmac_test_hmac384_vectors 7.200s 563.734us 1 1 100.00
hmac_test_hmac512_vectors 11.470s 1735.446us 1 1 100.00
hmac_stress_all 1481.610s 590165.329us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1481.610s 590165.329us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.670s 85.973us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.630s 24.677us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.930s 616.755us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.930s 616.755us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.190s 40.937us 1 1 100.00
hmac_csr_rw 0.830s 22.841us 1 1 100.00
hmac_csr_aliasing 4.540s 1392.960us 1 1 100.00
hmac_same_csr_outstanding 1.730s 200.090us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.190s 40.937us 1 1 100.00
hmac_csr_rw 0.830s 22.841us 1 1 100.00
hmac_csr_aliasing 4.540s 1392.960us 1 1 100.00
hmac_same_csr_outstanding 1.730s 200.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.960s 46.612us 1 1 100.00
hmac_tl_intg_err 2.070s 269.634us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.070s 269.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.620s 151.008us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.110s 158.020us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 71.600s 10485.612us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.950s 121.546us 1 1 100.00