Simulation Results

Simulation Results: i2c

23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.03 %

code
78.82 %

assert
97.46 %

func
81.82 %

line
96.54 %

branch
92.69 %

cond
85.87 %

toggle
73.17 %

FSM
45.83 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	13.080s	2756.353us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	22.390s	4940.572us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.830s	67.612us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	18.269us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.450s	2780.504us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.880s	715.415us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.840s	48.378us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	18.269us	1	1	100.00
	i2c_csr_aliasing	1.880s	715.415us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	1.220s	265.223us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	574.480s	19568.980us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	243.940s	12556.523us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.630s	45.966us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	79.380s	5548.623us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	28.220s	6725.196us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.020s	227.455us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.430s	427.038us	1	1	100.00
	i2c_host_fifo_reset_rx	2.640s	241.514us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	53.260s	3630.022us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	7.320s	1360.873us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.210s	258.742us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.900s	2085.621us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	575.930s	43739.602us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.880s	749.641us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	8.750s	3901.737us	1	1	100.00
	i2c_target_intr_smoke	4.590s	857.322us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.290s	159.220us	1	1	100.00
	i2c_target_fifo_reset_tx	1.060s	1278.559us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	6.080s	10460.605us	1	1	100.00
	i2c_target_stress_rd	8.750s	3901.737us	1	1	100.00
	i2c_target_intr_stress_wr	60.770s	13344.581us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.760s	3214.132us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	3.230s	10058.736us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.190s	12594.353us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	3.500s	10948.222us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.270s	1472.524us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.240s	1096.267us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	243.940s	12556.523us	1	1	100.00
	i2c_host_perf_precise	442.980s	24283.781us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	7.320s	1360.873us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.950s	108.712us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.170s	907.059us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.770s	432.734us	1	1	100.00
	i2c_target_nack_txstretch	1.630s	265.324us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.240s	608.001us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.690s	470.461us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.700s	44.102us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.920s	36.387us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.560s	313.699us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.560s	313.699us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.830s	67.612us	1	1	100.00
	i2c_csr_rw	1.000s	18.269us	1	1	100.00
	i2c_csr_aliasing	1.880s	715.415us	1	1	100.00
	i2c_same_csr_outstanding	1.250s	145.619us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.830s	67.612us	1	1	100.00
	i2c_csr_rw	1.000s	18.269us	1	1	100.00
	i2c_csr_aliasing	1.880s	715.415us	1	1	100.00
	i2c_same_csr_outstanding	1.250s	145.619us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.730s	95.482us	1	1	100.00
	i2c_sec_cm	1.230s	319.547us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.730s	95.482us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	11.920s	1043.586us	1
target_error_intr				1
	i2c_target_unexp_stop	1.120s	259.608us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	9.350s	2904.322us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_stress_all	54202922042496806157834249454320173681814708542291756425640932342361846690105	128	UVM_INFO @ 19568980454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	30854279614831824086552183111842903193997528383153186218888042574996233346484	97	UVM_INFO @ 2904321884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	772792569631735781519148370808612327539274144688050888049524981778337082275	84	UVM_INFO @ 2085620675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	28395371655700716137112661370160013897981560688944776252492437761934283155533	78	UVM_INFO @ 10058735780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	4845767547470064558142412984969895472431180350219522080313493928617973415850	78	UVM_INFO @ 259608065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	68886979740426768633848465190412219190084717879957116452821487426889672521868	79	UVM_INFO @ 10948222188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	9771925810873777078955879025926657017339196727202472957269886091833268095780	90	UVM_INFO @ 1043586158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access				1 test run
	i2c_host_mode_toggle	5746789462033342139491255359717081460453472213594221932300016838960177451811	86	src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584 The object at dereference depth 0 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.