Simulation Results: keymgr

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.59 %
  • code
  • 91.89 %
  • assert
  • 97.49 %
  • func
  • 64.39 %
  • line
  • 98.56 %
  • branch
  • 97.35 %
  • cond
  • 93.36 %
  • toggle
  • 84.13 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 3.850s 433.474us 1 1 100.00
random 1 1 100.00
keymgr_random 4.480s 278.397us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.530s 30.225us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.940s 140.585us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 4.880s 793.858us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 12.000s 1930.471us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.930s 38.877us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.940s 140.585us 1 1 100.00
keymgr_csr_aliasing 12.000s 1930.471us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 25.020s 3767.876us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 5.010s 124.845us 1 1 100.00
keymgr_sideload_kmac 10.140s 2270.575us 1 1 100.00
keymgr_sideload_aes 7.720s 456.781us 1 1 100.00
keymgr_sideload_otbn 5.030s 201.462us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 3.280s 824.787us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.510s 412.009us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.460s 140.345us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 5.800s 358.497us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 11.810s 1928.257us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 3.150s 116.765us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 10.600s 1123.852us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.880s 43.871us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 1.160s 27.147us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.340s 38.337us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.340s 38.337us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.530s 30.225us 1 1 100.00
keymgr_csr_rw 0.940s 140.585us 1 1 100.00
keymgr_csr_aliasing 12.000s 1930.471us 1 1 100.00
keymgr_same_csr_outstanding 1.610s 42.390us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.530s 30.225us 1 1 100.00
keymgr_csr_rw 0.940s 140.585us 1 1 100.00
keymgr_csr_aliasing 12.000s 1930.471us 1 1 100.00
keymgr_same_csr_outstanding 1.610s 42.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
keymgr_tl_intg_err 7.510s 273.723us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 3.200s 963.444us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 3.200s 963.444us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 3.200s 963.444us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 3.200s 963.444us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 12.700s 4756.381us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 7.510s 273.723us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 3.200s 963.444us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 25.020s 3767.876us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 4.480s 278.397us 1 1 100.00
keymgr_csr_rw 0.940s 140.585us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 4.480s 278.397us 1 1 100.00
keymgr_csr_rw 0.940s 140.585us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 4.480s 278.397us 1 1 100.00
keymgr_csr_rw 0.940s 140.585us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.510s 412.009us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 11.810s 1928.257us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 11.810s 1928.257us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 4.480s 278.397us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 3.380s 123.565us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.450s 88.745us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.510s 412.009us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.450s 88.745us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.450s 88.745us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.450s 88.745us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.200s 528.329us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.450s 88.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 5.360s 511.068us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 89116216957492544940801378430331826514436286743234283646211516003515315812412 647
UVM_INFO @ 511067750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---