Simulation Results: kmac/masked

 
23/07/2026 15:30:33 DVSim: v1.50.0 sha: 40dffb6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.21 %
  • code
  • 67.81 %
  • assert
  • 96.62 %
  • func
  • 76.21 %
  • line
  • 95.43 %
  • branch
  • 89.57 %
  • cond
  • 84.62 %
  • toggle
  • 28.92 %
  • FSM
  • 40.51 %
Validation stages
V1
100.00%
V2
68.97%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 1.780s 24.497us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.080s 155.822us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.030s 16.328us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 12.050s 447.127us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.120s 266.574us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.990s 338.575us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.030s 16.328us 1 1 100.00
kmac_csr_aliasing 5.120s 266.574us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.780s 39.346us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.350s 33.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1882.380s 27486.938us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 234.010s 7941.546us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 2583.260s 455308.857us 1 1 100.00
kmac_test_vectors_sha3_256 35.780s 5791.531us 1 1 100.00
kmac_test_vectors_sha3_384 1518.100s 148607.774us 1 1 100.00
kmac_test_vectors_sha3_512 1143.810s 212308.897us 1 1 100.00
kmac_test_vectors_shake_128 121.510s 4326.265us 1 1 100.00
kmac_test_vectors_shake_256 114.930s 9230.466us 1 1 100.00
kmac_test_vectors_kmac 2.600s 491.211us 1 1 100.00
kmac_test_vectors_kmac_xof 2.130s 118.208us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 157.290s 8620.909us 1 1 100.00
app 0 1 0.00
kmac_app 5.680s 145.168us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 2.060s 87.155us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 4.450s 307.610us 0 1 0.00
error 0 1 0.00
kmac_error 143.170s 12461.347us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.020s 41.894us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.060s 34.242us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 38.890s 9879.592us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.960s 37.914us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 0.770s 6.983us 0 1 0.00
lc_escalation 0 1 0.00
kmac_lc_escalation 15.070s 6128.673us 0 1 0.00
stress_all 0 1 0.00
kmac_stress_all 1.160s 17.365us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 1.050s 30.802us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.000s 33.672us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.850s 533.705us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.850s 533.705us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.080s 155.822us 1 1 100.00
kmac_csr_rw 1.030s 16.328us 1 1 100.00
kmac_csr_aliasing 5.120s 266.574us 1 1 100.00
kmac_same_csr_outstanding 1.330s 60.634us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.080s 155.822us 1 1 100.00
kmac_csr_rw 1.030s 16.328us 1 1 100.00
kmac_csr_aliasing 5.120s 266.574us 1 1 100.00
kmac_same_csr_outstanding 1.330s 60.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.180s 98.135us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.180s 98.135us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.180s 98.135us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.180s 98.135us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.330s 1326.223us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 36.650s 4434.481us 1 1 100.00
kmac_tl_intg_err 4.380s 382.449us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.380s 382.449us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
kmac_lc_escalation 15.070s 6128.673us 0 1 0.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 1.780s 24.497us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 157.290s 8620.909us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.180s 98.135us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 36.650s 4434.481us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 36.650s 4434.481us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 36.650s 4434.481us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 1.780s 24.497us 1 1 100.00
sec_cm_fsm_global_esc 0 1 0.00
kmac_lc_escalation 15.070s 6128.673us 0 1 0.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 36.650s 4434.481us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 6.410s 797.678us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 1.780s 24.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 8.450s 1767.439us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 8 test runs
kmac_sideload_invalid 48302321625611571572025210022426681039004677104835063426663307502205151680729 76
UVM_INFO @ 34242416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app 23439912025536327319378094027237758123845365346710773266802875305356174964102 79
UVM_INFO @ 145167516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 82548571388936546595232731011562075714506296156019504768267617906213963672488 78
UVM_INFO @ 87155170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 111223888590772745054030705319471688226315716285958283133847517303235229726093 79
UVM_INFO @ 307610001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 22423951512705548038389247255453580584880015878246813353164631096058325846465 153
UVM_INFO @ 12461347058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_lc_escalation 31381305893247831806400836302196361575627344756905185055028635958748472022566 87
UVM_INFO @ 6128672668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 76416278278127682591321963793937497297781349124263168718451813409351225811174 79
UVM_INFO @ 17364741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 102871898011124689734312807306625684363953244243367060104938076436693803259887 104
UVM_INFO @ 1767438505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_key_error 32760408538205939053129672833749435228590464120627173257915290974801007642357 78
UVM_ERROR @ 41893942 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 41893942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 81185441232239865633670575017275160337318962857639522882781577064991260132147 78
UVM_ERROR @ 6982504 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 6982504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 1 test run
kmac_mubi 75864679361143622805049687670819386013524631606567360513156100385660966218441 79
UVM_INFO @ 797677682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---